5秒后页面跳转
捷配首页

Datasheet > 88K8483BRI
88K8483BRI PDF预览

88K8483BRI

更新时间： 2024-10-01 20:03:23
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
162页 2069K
描述
Microprocessor Circuit, PBGA672, ROHS COMPLIANT, FCBG-672

阅读下载

中文翻译

获取价格

88K8483BRI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：ROHS COMPLIANT, FCBG-672针数：672
Reach Compliance Code：not_compliantECCN代码：5A991
HTS代码：8542.39.00.01风险等级：5.82
JESD-30 代码：S-PBGA-B672JESD-609代码：e1
长度：27 mm湿度敏感等级：4
端子数量：672最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA672,26X26,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：260电源：1.2,1.5,2.5,3.3 V
认证状态：Not Qualified座面最大高度：3.22 mm
子类别：Other Microprocessor ICs最大供电电压：1.32 V
最小供电电压：1.08 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：27 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

88K8483BRI 数据手册

 浏览型号88K8483BRI的Datasheet PDF文件第2页浏览型号88K8483BRI的Datasheet PDF文件第3页浏览型号88K8483BRI的Datasheet PDF文件第4页浏览型号88K8483BRI的Datasheet PDF文件第5页浏览型号88K8483BRI的Datasheet PDF文件第6页浏览型号88K8483BRI的Datasheet PDF文件第7页 
IDT88K8483  
SPI-4 Exchange  
Document Issue 1.0  
Description  
Features  
◆
Functionality  
The IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4  
Exchange devices build on IDT’s proven SPI-4 implementation and  
packet fragment processor (PFP) design. The IDT88K8483 suits appli-  
cations with slow backpressure response and other advanced  
networking applications when there is the need for duplicate ports to re-  
route data multiple times through the packet-exchange and temporary  
storage for complete in-flight packets.  
–
–
–
Multiplexes logical ports (LPs) from SPI-4A and SPI-4B to SPI-  
4M  
Optionally converts between interleaved packet transfers and  
whole packet transfers per logical port  
Data redirection per LP between SPI-4A, SPI-4B and 10G  
FPGA  
–
–
–
Per LP configurable memory allocation  
Per LP memory expansion via QDR-II SRAM interface  
3 separate clock generators allowing fully flexible, fully inte-  
grated clock derivations and generation  
The data on each SPI-4 interface logical port (LP) are mapped to a  
logical identifier (LID). A data flow between logical port addresses on the  
various interfaces is accomplished using LID maps that can be dynami-  
cally reconfigured. The device enables the connection of two SPI-4  
devices to a network processor having one or more SPI-4 interfaces. Up  
to 18Mbit of additional buffer memory can be provided using the QDRII  
interface. Alternatively, the HSTL I/O may be used to provide a generic  
packet interface to a FPGA. The device supports a maximum of 128  
logical ports.  
◆
Standard Interfaces  
–
Two OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range, 64  
concurrently active LPs per interface  
–
One OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range,  
128 concurrently active LPs  
–
–
–
SPI-4 FIFO status channel options:  
LVDS full-rate, LVDS quarter-rate, LVTTL quarter-rate  
SPI-4 compatible with Network Processor Streaming Interface  
(NPSI NPE-Framer mode of operation)  
Applications  
–
HSTL Interface with selectable operating mode  
–
–
–
–
–
–
Ethernet transport  
160 - 200 MHz DDR packet interface, 64 concurrently active  
LPs; or  
SONET / SDH packet transport line cards  
Broadband aggregation  
Multi-service switches  
IP services equipment  
Security firewalls  
QDR-II memory interface: 160 - 200MHz HSTL  
Serial or parallel microprocessor interface for control and  
monitoring  
–
–
IEEE 1491.1 JTAG  
Block Diagram  
Auxiliary  
10Gbps  
Interface  
QDR-II 10Gbps  
Memory int.  
10Gbps FPGA  
Packet Int.  
Serial / 8bit  
Micro.  
Int.  
MicroprocessorInterface  
Packet Fragment  
Processor A-TM (PFP)  
SPI-4A  
64 Logical  
Ports  
SPI-4M  
128 Logical  
Ports  
Packet Fragment  
Tributary  
SPI-4s  
Main  
SPI-4  
Processor A-MT (PFP)  
Packet Fragment  
Processor B-TM (PFP)  
SPI-4B  
64 Logical  
Ports  
Packet Fragment  
Processor B-MT (PFP)  
JTAG Interface  
JTAG Int.  
Figure 1 IDT88K8483 Block Diagram  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 162  
October 20, 2006  
DSC 6214/-  
© 2006 Integrated Device Technology, Inc.  
1234567...162

中文翻译

下载PDF

与88K8483BRI相关器件

型号 品牌 获取价格 描述 数据表
88M2001-2 GRAYHILL

获取价格

 		Sealed Keypads
88M2009-2 GRAYHILL

获取价格

 		Sealed Keypads
88M2012-1 GRAYHILL

获取价格

 		Sealed Keypads
88M2015-1 GRAYHILL

获取价格

 		Sealed Keypads
88M2018-1 GRAYHILL

获取价格

 		Sealed Keypads
88M2019-1 GRAYHILL

获取价格

 		Sealed Keypads
88N18G-AD4-R UTC

获取价格

 		Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO4, SOT-143, 4 PIN
88N18G-AE5-R UTC

获取价格

 		Power Supply Support Circuit,
88N18G-AF5-R UTC

获取价格

 		Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO5, SOT-25, 5 PIN
88N18L-AD4-R UTC

获取价格

 		Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO4, SOT-143, 4 PIN

与88K8483BRI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证