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85411AMLFT PDF预览

85411AMLFT

更新时间: 2024-09-26 01:16:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 230K
描述
Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

85411AMLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.88
系列:85411输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:2.5 ns传播延迟(tpd):2.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.02 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

85411AMLFT 数据手册

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Low Skew, 1-to-2 Differential-to-LVDS  
Fanout Buffer  
85411  
Data Sheet  
GENERAL DESCRIPTION  
FEATURES  
Two differential LVDS outputs  
The 85411 is a low skew, high performance 1-to-2 Differential-  
to-LVDS Fanout Buffer and a member of the family of High  
Performance Clock Solutions from IDT. The CLK, nCLK pair  
can accept most standard differential input levels.The 85411 is  
characterized to operate from a 3.3V power supply. Guaranteed  
output and part-to-part skew characteristics make the 85411 ideal  
for those clock distribution applications demanding well defined  
performance and repeatability.  
One differential CLK, nCLK clock input  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Maximum output frequency: 650MHz  
Translates any single ended input signal to  
LVDS levels with resistor bias on nCLK input  
Output skew: 20ps (maximum)  
Part-to-part skew: 250ps (maximum)  
Additive phase jitter, RMS: 0.05ps (typical)  
Propagation delay: 2.5 ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in lead free (RoHS 6) package  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
Q0  
nQ0  
Q1  
VDD  
1
2
3
4
8
7
6
5
Pullup  
CLK  
Pulldown  
nCLK  
CLK  
nCLK  
GND  
Q1  
nQ1  
nQ1  
85411  
8-Lead SOIC  
3.90mm x 4.90mm x 1.37mm package body  
M Package  
Top View  
©2016 Integrated Device Technology, Inc  
1
Revision C January 20, 2016  

85411AMLFT 替代型号

型号 品牌 替代类型 描述 数据表
85411AMILFT IDT

类似代替

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer
85411AMILF IDT

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Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

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