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85104AGI PDF预览

85104AGI

更新时间: 2024-01-10 04:22:37
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 356K
描述
Low Skew Clock Driver, 85104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 MM X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

85104AGI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:6.50 MM X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
系列:85104输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:3.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

85104AGI 数据手册

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LOW SKEW, 1-TO-4, DIFFERENTIAL/  
LVCMOS-TO-0.7V HCSL FANOUT BUFFER  
ICS85104I  
GENERAL DESCRIPTION  
FEATURES  
The ICS85104I is a low skew, high performance 1-  
Four 0.7V differential HCSL outputs  
ICS  
HiPerClockS™  
to-4 Differential/LVCMOS-to-0.7V HCSL Fanout  
Selectable differential CLK0, nCLK0 or LVCMOS inputs  
Buffer and a member of the HiPerClockSfamily  
of High Performance Clock Solutions from IDT.  
The ICS85104I has two selectable clock inputs.  
CLK0, nCLK0 pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
The CLK0, nCLK0 pair can accept most standard differential  
input levels. The single-ended CLK1 can accept LVCMOS or  
LVTTL input levels. The clock enable is internally synchronized  
to eliminate runt clock pulses on the outputs during asynchro-  
nous assertion/deassertion of the clock enable pin.  
CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
Maximum output frequency: 500MHz  
Translates any single-ended input signal to 3.3V  
HCSL levels with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics make  
the ICS85104I ideal for those applications demanding well  
defined performance and repeatability.  
Output skew: 100ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Propagation delay: 3.2ns (maximum)  
Additive phase jitter, RMS: 0.22ps (typical)  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
GND  
CLK_EN  
CLK_SEL  
CLK0  
nCLK0  
CLK1  
nc  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Q0  
nQ0  
VDD  
Q1  
nQ1  
Q2  
nQ2  
VDD  
Q3  
Pullup  
CLK_EN  
D
Q
Pulldown  
Pullup/Pulldown  
LE  
CLK0  
nCLK0  
0
1
nc  
IREF  
VDD  
Q0  
nQ0  
nQ3  
Pulldown  
Pulldown  
CLK1  
Q1  
nQ1  
ICS85104I  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.925mm Package Body  
G Package  
CLK_SEL  
Q2  
nQ2  
IREF  
Q3  
nQ3  
Top View  
IDT/ ICS0.7V HCSL FANOUT BUFFER  
1
ICS85104AGI REV. A FEBRUARY 25, 2009  

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