Datasheet > 85104I

85104I

更新时间： 2022-02-26 12:13:33

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	222K
描述
Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

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85104I 数据手册

Low Skew, 1-to-4, Differential/LVCMOS-to-

0.7V HCSL Fanout Buffer

85104I

Data Sheet

GENERAL DESCRIPTION

FEATURES

The 85104I is a low skew, high performance 1-to-4 Differential/

LVCMOS-to-0.7V HCSL Fanout Buffer.The 85104I has two select-

able clock inputs.The CLK0, nCLK0 pair can accept most standard

differential input levels.The single-ended CLK1 can accept LVCMOS

or LVTTL input levels. The clock enable is internally synchronized

to eliminate runt clock pulses on the outputs during asynchronous

assertion/deassertion of the clock enable pin.

• Four 0.7V differential HCSL outputs

• Selectable differential CLK0, nCLK0 or LVCMOS inputs

• CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

• CLK1 can accept the following input levels:

LVCMOS or LVTTL

Guaranteed output and part-to-part skew characteristics

make the 85104I ideal for those applications demanding well

deﬁned performance and repeatability.

• Maximum output frequency: 500MHz

• Translates any single-ended input signal to 3.3V

HCSL levels with resistor bias on nCLK input

• Output skew: 100ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Propagation delay: 3.2ns (maximum)

• Additive phase jitter, RMS: 0.22ps (typical)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

BLOCK DIAGRAM

PIN ASSIGNMENT

Pullup

CLK_EN

Pulldown

Pullup/Pulldown

CLK0

nCLK0

nQ0

Pulldown

CLK1

nQ1

85104I

20-Lead TSSOP

CLK_SEL

nQ2

6.5mm x 4.4mm x 0.925mm Package Body

G Package

IREF

nQ3

Top View

Revision A January 20, 2016

12 3 4 5 6 7...17

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