Datasheet > 85102AGIT

85102AGIT

更新时间： 2024-01-30 01:38:05

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
16页	347K
描述
Low Skew Clock Driver, 85102 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16

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85102AGIT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	4.40 MM X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16	针数：	16
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.38
系列：	85102	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	5 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	2	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	225	电源：	3.3 V
Prop。Delay @ Nom-Sup：	3.2 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

85102AGIT 数据手册

ICS85102I

LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, V_DD= 3.3V 10ꢀ, TA = -40°C TO 85°C

Symbol Parameter

f_MAXOutput Frequency

Test Conditions

CLK_SEL = 0

CLK_SEL = 1

CLK_SEL = 0

CLK_SEL = 1

Minimum Typical Maximum Units

500

250

3.2

2.8

MHz

2.0

t_PD

Propagation Delay; NOTE 1

tsk(o)

Output Skew; NOTE 2, 4

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

600

100MHz (12kHz - 20MHz)

250MHz (12kHz - 20MHz)

0.22

0.14

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

tjit

Absolute Maximum Output Voltage;

NOTE 5, 10

Absolute Minimum Output Voltage;

NOTE 5, 11

V_MAX

V_MIN

1150

100

-300

V_RB

Ringback Voltage; NOTE 6, 13

-100

500

250

t_STABLE

V_CROSS

Time before V_RBis allowed; NOTE 6, 13

Absolute Crossing Voltage; NOTE 5, 8, 9

550

140

Total Variation of V_CROSSover all edges;

NOTE 5, 8, 12

ΔV_CROSS

Measured between

-150mV to +150mV

Rise/Fall Edge Rate; NOTE 6, 7

0.6

5.5

V/ns

ꢀ

odc

Output Duty Cycle; NOTE 14

All parameters measured at ƒ≤ 250MHz unless noted otherwise.

NOTE 1: Measured from the V_DD/2 of the input to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output

differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: Measurement taken from single-ended waveform.

NOTE 6: Measurement taken from differential waveform.

NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be

monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential

zero crossing. See Parameter Measurement Information Section.

NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

See Parameter Measurement Information Section.

NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all

crossing points for this measurement. See Parameter Measurement Information Section.

NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.

NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.

NOTE 12: Defined as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance

in the V_CROSSfor any particular system. See Parameter Measurement Information Section.

NOTE: 13. T_STABLEis the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges

before it is allowed to droop back into the V_RB100mV differential range. See Parameter Measurement Information Section.

NOTE 14: Input duty cycle must be 50ꢀ.

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85102AGI REV. A JUNE 10, 2008

1 2 3 456 7 8...16

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