849S625 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1,
2
XTAL_IN
XTAL_OUT
Input
Power
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3, 12, 31, 46
VEE
Negative supply pins.
4,
5
SELC0,
SELC1
Selects the output divider value. See Table 3D.
LVCMOS/LVTTL interface levels.
Pulldown
Active high output enable. When logic HIGH, Bank A outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
6
7, 48
8
OEA
VCC
Input
Power
Input
Pullup
Pullup
Core supply pins.
Active high output enable. When logic HIGH, Bank B outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
OEB
Active high output enable. When logic HIGH, Bank C outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
9
OEC
Input
Pullup
10,
11
SELB0,
SELB1
Selects the output divider value. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Pulldown
13, 19, 24,
32, 37
VCCO
Power
Output supply pins.
14, 15
16, 17
18
nQC1, QC1
nQC0, QC0
nc
Output
Output
Unused
Output
Output
Output
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
No connect.
20, 21
22, 23
25, 26
27, 28
29, 30
33, 34
35, 36
38, 39
40
nQB1, QB1
nQB0, QB0
nQA5, QA5
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
VCCA
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Analog supply pin.
41,
42
SELA1,
SELA0
Selects the output divider value. See Table 3B.
LVCMOS/LVTTL interface levels.
Input
Pulldown
Selects between either LVDS or LVPECL output levels. See Table 3A.
LVCMOS/LVTTL interface levels.
43
44
45
47
SEL_OUT
MR
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Master Reset. LVCMOS/LVTTL interface levels.
PLL BYPASS mode select pin. See Table 3F.
LVCMOS/LVTTL interface levels.
BYPASS
REF_CLK
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulludown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2015 Integrated Device Technology, Inc
3
December 2, 2015
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