FemtoClock® NG Crystal-to-LVDS
Clock Synthesizer
844N255I
Data Sheet
General Description
Features
The 844N255I is a 6-output clock synthesizer designed for wireless
infrastructure clock applications. The device uses IDT’s fourth
generation FemtoClock® NG technology for an optimum of high
clock frequency and low phase noise performance, combined with a
low power consumption and high power supply noise rejection. The
reference frequency is selectable and the following frequency is
supported: 25MHz. The synthesizer generates selectable
156.25MHz, 125MHz, 100MHz, 50MHz and 25MHz clock signals.
The device is optimized for very low phase noise and cycle to cycle
jitter. The synthesized clock frequency and the phase-noise
performance are optimized for driving SRIO 1.3 and 2.0 SerDes
reference, DSP and host-processor clocks. The device supports a
2.5V voltage supply and is packaged in a small, lead-free (RoHS 6)
48-lead VFQFN package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements.
• 4TH generation FemtoClock® NG technology
• Selectable 156.25MHz, 125MHz, 100MHz, 50MHz and 25MHz
output clock signals synthesized from a 25MHz reference
frequency
• Six differential LVDS clock outputs
• Crystal interface designed for a 25MHz crystal
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
• Internal regulator for optimum noise rejection
• LVCMOS interface levels for the frequency select and output
enable inputs
• Full 2.5V supply voltage
• Lead-free (RoHS 6) 48-lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
XTAL_IN
25MHz
0
OSC
PFD
&
FemtoClock® NG
VCO
÷16
QA
nQA
XTAL_OUT
25MHz
1
Pulldown
÷20,
÷25
÷M
QB0
Pulldown
Pulldown
÷20,
÷25
nQB0
REF_CLK
÷50,
÷100
QB1
nQB1
Pulldown
Pullup
REF_SEL
MSEL
÷50
Pulldown
Pullup
÷100
QC
nQC
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
FSELB
FSELC
FSELD
5
QD
©2016 Integrated Device Technology, Inc
1
April 28, 2016