Datasheet > 84330AY-03LF

84330AY-03LF

更新时间： 2024-02-21 23:12:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	314K
描述
Clock Generator, PQFP32

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技术参数
数据手册

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84330AY-03LF 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.84
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
湿度敏感等级：	3	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

84330AY-03LF 数据手册

ICS84330-03

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated

Circuit

Systems, Inc.

FUNCTIONAL DESCRIPTION

The programmable features of the ICS84330-03 support

two input modes to program the M divider and N output

divider. The two input operational modes are parallel and

I²C. Figure 1 shows the timing diagram for parallel mode. In

parallel mode the nP_LOAD input is LOW. The data on

inputs M0 through M8 and N0 through N1 is passed

directly to the M divider and N output divider. On the LOW-

to-HIGH transition of the nP_LOAD input, the data is latched

and the M divider remains loaded until the next LOW tran-

sition on nP_LOAD or until an I²C event occurs. The rela-

tionship between the VCO frequency, the crystal frequency

NOTE: The functional description that follows describes op-

eration using a 16.6667MHz crystal. Valid PLL loop divider

values for different crystal or input frequencies are defined

in the Input Frequency Characteristics, Table 7, NOTE 1.

The ICS84330-03 features a fully integrated PLL and

therefore requires no external components for setting the

loop bandwidth. A quartz crystal is used as the input to the

on-chip oscillator. The output of the oscillator is divided by

16 prior to the phase detector.

fxtal

and the M divider is defined as follows:

The phase detector and the M divider force the VCO output

frequency to be 2M times the reference frequency by

adjusting the VCO control voltage. Note that for some

values of M (either too high or too low), the PLL will not

achieve lock. The output of the VCO is scaled by a divider

prior to being sent to each of the LVPECL output buffers.

The divider provides a 50ꢀ output duty cycle.

fVCO =

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Func-

tion Table. Valid M values for which the PLL will achieve

lock are defined as 120 ≤ M ≤ 336. The frequency out is

fVCO fxtal 2M

defined as follows:

fout

PARALLEL

M, N

M0:M8, N0:N1

nP_LOAD

Time

FIGURE 1. PARALLEL LOAD OPERATIONS

84330AY-03

www.icst.com/products/hiperclocks.html

REV.A FEBRUARY 2, 2006

1 2 3 456 7 8...20

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