Datasheet > 842023AGLFT

842023AGLFT

更新时间： 2024-01-10 19:57:32

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
12页	757K
描述
Clock Generator, PDSO8

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技术参数
数据手册

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842023AGLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.84
JESD-30 代码：	R-PDSO-G8	端子数量：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	2.5/3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	84 mA	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

842023AGLFT 数据手册

ICS842023

FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR

PRELIMINARY

Application Information

Crystal Input Interface

The ICS842023 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 1 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

XTAL_IN

22p

18pF Parallel Crystal

XTAL_OUT

22p

Figure 1. Crystal Input Interface

LVCMOS to XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 2. The XTAL_OUT pin can be left floating. The

input edge rate can be as slow as 10ns. For LVCMOS inputs, it is

recommended that the amplitude be reduced from full swing to half

swing in order to prevent signal interference with the power rail and

to reduce noise. This configuration requires that the output

impedance of the driver (Ro) plus the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination

at the crystal input will attenuate the signal in half. This can be

done in one of two ways. First, R1 and R2 in parallel should equal

the transmission line impedance. For most 50Ω applications, R1

and R2 can be 100Ω. This can also be accomplished by removing

R1 and making R2 50Ω.

VCC

0.1µf

50Ω

XTAL_IN

Zo = Ro + Rs

XTAL_OUT

Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface

IDT™ / ICS™ HSTL CLOCK GENERATOR

ICS842023AG REV. B JULY 15, 2008

1...3 4 567 8 9...12

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