Datasheet > 8402AYLFT

8402AYLFT

更新时间： 2024-01-05 07:57:01

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
17页	365K
描述
TQFP-32, Reel

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8402AYLFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.68
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	7 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	350 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	2.5/3.3,3.3 V	主时钟/晶体标称频率：	40 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Clock Generators	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

8402AYLFT 数据手册

ICS8402

Integrated

Circuit

ICS8402

_{350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHE}3_SI5_ZE0_RMHZ, CRYSTAL-TO-LVCMOS / LVTT_TL_SD

Systems, Inc.

FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes op- put divider to a specific default state that will automatically

eration using a 25MHz crystal. Valid PLL loop divider values occur during power-up. The TEST output is LOW when op-

for different crystal or input frequencies are defined in the erating in the parallel input mode. The relationship between

Input Frequency Characteristics, Table 5, NOTE 1.

the VCO frequency, the crystal frequency and the M divider

is defined as follows: fVCO = fxtal x M

The ICS8402 features a fully integrated PLL and therefore

requires no external components for setting the loop band- The M value and the required values of M0 through M8 are

width. A fundamental crystal is used as the input to the on- shown in Table 3B, Programmable VCO Frequency Function

chip oscillator.The output of the oscillator is fed into the phase Table.Valid M values for which the PLL will achieve lock for a

detector. A 25MHz crystal provides a 25MHz phase detector 25MHz reference are defined as 10 ≤ M ≤ 28.The frequency

reference frequency. The VCO of the PLL operates over a out is defined as follows: FOUT = fVCO = fxtal x M

range of 250MHz to 700MHz. The output of the M divider is

also applied to the phase detector.

Serial operation occurs when nP_LOAD is HIGH and

S_LOAD is LOW. The shift register is loaded by sampling

The phase detector and the M divider force the VCO output the S_DATA bits with the rising edge of S_CLOCK. The con-

frequency to be M times the reference frequency by adjusting tents of the shift register are loaded into the M divider and N

the VCO control voltage. Note that for some values of M (either output divider when S_LOAD transitions from LOW-to-HIGH.

too high or too low), the PLL will not achieve lock.The output of The M divide and N output divide values are latched on the

the VCO is scaled by a divider prior to being sent to each of HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,

the LVCMOS output buffers. The divider provides a 50% out- data at the S_DATA input is passed directly to the M divider

put duty cycle.

and N output divider on each rising edge of S_CLOCK. The

serial mode can be used to program the M and N bits and

The programmable features of the ICS8402 support two in- test bits T1 and T0. The internal registers T0 and T1 deter-

mine the state of the TEST output as follows:

put modes to program the M divider and N output divider.

The two input operational modes are parallel and serial. Fig-

ure 1 shows the timing diagram for each mode. In parallel

mode, the nP_LOAD input is initially LOW. The data on in-

puts M0 through M8 and N0 and N1 is passed directly to the

M divider and N output divider. On the LOW-to-HIGH transi-

tion of the nP_LOAD input, the data is latched and the M

divider remains loaded until the next LOW transition on

nP_LOAD or until a serial event occurs. As a result, the M

and N bits can be hardwired to set the M divider and N out-

T1 T0

TEST Output

LOW

Shift Register Output

Output of M divider

CMOS Fout

SERIAL

OADING

S_CLOCK

S_DATA

*NULL

S_LOAD

nP_LOAD

PARALLEL LOADING

M, N

M0:M8, N0:N1

nP_LOAD

S_LOAD

Time

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

*NOTE: The NULL timing slot must be observed.

www.icst.com/products/hiperclocks.html

8402AY

REV.C SEPTEMBER 1, 2005

IDT™ / ICS™ 350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER

ICS8402

123 4 5 6 7...17

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