Datasheet > 82V3202NLG8

82V3202NLG8

更新时间： 2024-01-22 04:47:04

品牌	Logo	应用领域
艾迪悌 - IDT		电信电信集成电路
页数	文件大小	规格书
117页	1222K
描述
Telecom Circuit, 1-Func, PQCC68, GREEN, PLASTIC, VFQFPN-68

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82V3202NLG8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	GREEN, PLASTIC, VFQFPN-68
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.83
JESD-30 代码：	S-PQCC-N68	JESD-609代码：	e3
长度：	10 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	68
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	座面最大高度：	1 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

IDT82V3202

EBU WAN PLL

performance without being affected by operating conditions or silicon

process variations.

DESCRIPTION

The IDT82V3202 is an integrated, single-chip solution for the Syn-

chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4

clocks in SONET / SDH equipments, DWDM and Wireless base station,

such as GSM, 3G, DSL concentrator, Router and Access Network appli-

cations.

If the DPLL outputs are processed by T0/T4 APLL, the outputs of the

device will be in a better jitter/wander performance.

The device provides programmable DPLL bandwidths: 0.1 Hz to 560

Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-

tings cover all SONET / SDH clock synchronization requirements.

The device supports three types of input clock sources: recovered

clock from STM-N or OC-n, PDH network synchronization timing and

external synchronization reference timing.

A high stable input is required for the master clock in different appli-

cations. The master clock is used as a reference clock for all the internal

circuits in the device. It can be calibrated within ±741 ppm.

An input clock is automatically or manually selected for DPLL lock-

ing. The DPLL supports three primary operating modes: Free-Run,

Locked and Holdover. In Free-Run mode, the DPLL refers to the master

clock. In Locked mode, the DPLL locks to the selected input clock. In

Holdover mode, the DPLL resorts to the frequency data acquired in

Locked mode. Whatever the operating mode is, the DPLL gives a stable

All the read/write registers are accessed only through an I C pro-

gramming interface.

The device can be used typically in Line Card application.

Description

September 11, 2009

1...7 8 91011 12 13...117

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