ENHANCED T1/E1/OC3 WAN PLL
WITH DUAL REFERENCE INPUTS
IDT82V3155
FEATURES
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Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
Holdover frequency accuracy of 0.025 ppm
Phase slope of 5 ns per 125 µs
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56-pin SSOP (Green option available)
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Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and
155.52 Mbit/s application
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Supports ITU-T G.813 Option 1 clocks
Supports ITU-T G.812 Type IV clocks
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
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Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o, C32o and
C155 output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o,
F19o,F32o, RSP and TSP
FUNCTIONAL BLOCK DIAGRAM
TDO TDI
OSCi
TCLR RST
VDDD VSS VDDD VSS VDDD VSS VDDA
VDDA
VSS VSS
C2/C1.5
TCK
TMS
C32o
C19o
JTAG
OSC
C155POS
C155NEG
TRST
Virtual
Reference
C16o
C8o
C4o
C2o
Reference Input
Switch
TIE Control
Block
Fref0
Fref1
IN_sel
C3o
C1.5o
C6o
DPLL
FLOCK
F0o
F8o
Reference Input
Monitor 0
MON_out0
MON_out1
F16o
F19o
F32o
RSP
TSP
Feedback Signal
Reference Input
Monitor 1
LOCK
Invalid Input
Signal Detection
F0_sel0
F0_sel1
Frequency
Select Circuit 0
State Control Circuit
F1_sel0
F1_sel1
Frequency
Select Circuit 1
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
May 24, 2006
DSC-6244/3
2006 Integrated Device Technology, Inc.