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813323BGLFT

更新时间： 2023-07-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管外围集成电路
页数 文件大小 规格书
22页 835K
描述
Clock Generator, CMOS, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24

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813323BGLFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.22
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：7.8 mm端子数量：24
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5,3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大压摆率：130 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

813323BGLFT 数据手册

 浏览型号813323BGLFT的Datasheet PDF文件第2页浏览型号813323BGLFT的Datasheet PDF文件第3页浏览型号813323BGLFT的Datasheet PDF文件第4页浏览型号813323BGLFT的Datasheet PDF文件第5页浏览型号813323BGLFT的Datasheet PDF文件第6页浏览型号813323BGLFT的Datasheet PDF文件第7页 
VCXO Jitter Attenuator &  
FemtoClock™Multiplier  
ICS813323  
DATA SHEET  
General Description  
Features  
The ICS813323 is a PLL based synchronous multiplier  
that is optimized for SONET clock jitter attenuation and  
frequency translation. The device contains two internal  
frequency multiplication stages which are cascaded in  
series. The first stage is a VCXO PLL that is optimized  
• Three differential LVPECL output pairs  
S
IC  
• One differential input supports the following input types:  
HiPerClockS™  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• Accepts input frequencies from 19.44MHz to 622.08MHz,  
including: 77.76MHz and 155.52MHz input clocks  
to provide reference clock jitter attenuation. The second stage is a  
FemtoClock™ frequency multiplier that provides a low jitter, high  
frequency SONET output clock.  
• Attenuates the phase jitter of the input clock by using a low-cost  
pullable fundamental mode VCXO crystal  
• Outputs common SONET clock rates  
Pre-divider and output divider multiplication ratios are selected using  
device selection control pins. The multiplication ratios are optimized  
to support most common clock rates used in SONET applications.  
The VCXO requires the use of an external, inexpensive pullable  
crystal. The VCXO uses external passive loop filter components  
which allows configuration of the PLL loop bandwidth and damping  
characteristics.  
• VCXO PLL bandwidth can be optimized for jitter attenuation  
and reference tracking using external loop filter connection  
• Absolute pull range: 50ppm  
• FemtoClock frequency multiplier provides low jitter,  
high frequency output  
• FemtoClock frequency: 622.08MHz  
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal  
Pin Assignment  
(12kHz – 20MHz): 1.4ps (typical)  
• Full 3.3V supply, or mixed 3.3V core/2.5V output supply  
• 0°C to 70°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
1
2
24  
23  
OE  
VCCO  
LF  
VCCA  
nQ2  
Q2  
22  
21  
VCC  
VCCO  
3
4
5
6
7
20  
19  
18  
17  
nQ1  
Q1  
FSEL0  
VEE  
nQ0  
Q0  
PSEL0  
VEE  
8
9
FSEL1  
nBYPASS  
CLK  
PSEL1  
XTAL_OUT  
XTAL_IN  
VEE  
16  
15  
14  
13  
10  
11  
12  
nCLK  
ICS813323  
24 Lead TSSOP  
4.4mm x 7.8mm x 0.925mm package body  
G Package  
Top View  
Block Diagram  
External  
Loop Filter Input  
Q0  
Pullup  
19.44MHz  
nBypass  
0
1
nQ0  
Q1  
Output  
Divider  
1, 4, 8, 32  
Pulldown  
CLK  
Phase Detector  
Loop Filter  
Pre-Divider  
1, 4, 8, 32  
VCO  
Phase  
Detector  
VCXO  
19.44MHz  
622.08MHz  
Pullup/Pulldown  
nCLK  
nQ1  
Q2  
2
Pullup  
PSEL[1:0]  
÷32  
VCXO Jitter Attenuation PLL  
FemtoClock Frequency Multiplier  
nQ2  
2
Pullup  
Pullup  
FSEL[1:0]  
OE  
ICS813323BG REVISION A APRIL 13, 2010  
1
©2010 Integrated Device Technology, Inc.  
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