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810001BK-21LFT

更新时间： 2024-09-30 14:40:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 3806K
描述
PLL Based Clock Driver, 810001 Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32

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810001BK-21LFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.4系列：810001
输入调节：MUXJESD-30 代码：S-XQCC-N32
JESD-609代码：e3长度：5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：32
实输出次数：1最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：5 mm
最小 fmax：175 MHzBase Number Matches：1

810001BK-21LFT 数据手册

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PRELIMINARY  
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL  
ICS810001-21  
General Description  
Features  
The ICS810001-21 is a member of the HiperClockS™  
• Accepts various HD and SD references including hsync,  
transport and pixel clock rates  
S
IC  
family of high performance clock solutions from IDT.  
The ICS810001-21 is a PLL based synchronous  
clock generator that is optimized for digital video  
clock jitter attenuation and frequency translation.  
HiPerClockS™  
• Outputs HD and SD pixel rates  
• One LVCMOS/LVTTL PLL clock output  
• Two selectable LVCMOS/LVTTL input clocks  
• LVCMOS input select lines  
The device contains two internal frequency multiplication stages  
that are cascaded in series. The first stage is a VCXO PLL that is  
optimized to provide reference clock jitter attenuation, and to  
support the complex PLL multiplication ratios needed for video  
rate conversion. The second stage is a FemtoClock frequency  
multiplier that provides the low jitter, high frequency video output  
clock.  
• VCXO PLL bandwidth can be optimized for jitter attenuation and  
reference tracking  
• FemtoClock frequency multiplier provides low jitter, high  
frequency output  
• FemtoClock range: 560MHz - 700MHz  
Preset multiplication ratios are selected from internal lookup  
tables using device input selection pins. The multiplication ratios  
are optimized to support most common video rates used in  
professional video system applications. The VCXO requires the  
use of an external, inexpensive pullable crystal. Two crystal  
connections are provided (pin selectable) so that both 60 and  
59.94 base frame rates can be supported. The VCXO requires  
external passive loop filter components which are used to set the  
PLL loop bandwidth and damping characteristics.  
• RMS phase jitter @148.3516484MHz, using a 26.973027MHz  
crystal (12kHz - 20MHz): 1.089ps (typical)  
• 3.3V supply voltage  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Output Rates Supported  
Pin Assignment  
Frequency (MHz)  
27  
Application  
MPEG Transport, ITU-R601, CCIR 656  
27MHz x 1000/1001  
26.973027  
74.25  
32 31 30 29 28 27 26 25  
SMPTE 292M/60  
1
2
3
4
5
6
7
8
LF1  
N0  
24  
23  
22  
21  
74.17582418  
148.5  
SMPTE 292M/59.94  
LF0  
ISET  
N1  
SMPTE 292M/60, 1080P  
SMPTE 292M/59.94, 1080P  
SMPTE 292M Level “D”  
nBP1  
OE  
VDD  
148.3516484  
36  
nBP0  
20 GND  
GND  
Q
19  
18  
17  
CLK_SEL  
CLK1  
VDDO  
VDDA  
Example Frequency Conversions:  
9
10 11 12 13 14 15 16  
All nine combinations from/to:  
27MHz  
74.175MHz  
74.25MHz  
NTSC or PAL hsync to 27MHz  
NTSC or PAL hsync to 4xFsc  
ICS810001-21  
32 Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization  
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ DUAL VCXO VIDEO PLL  
1
ICS810001DK-21 REV. C OCTOBER 8, 2008  
1234567...17

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