Datasheet > 80C51GB

80C51GB

更新时间： 2024-02-06 21:17:26

品牌	Logo	应用领域
英特尔 - INTEL		微控制器
页数	文件大小	规格书
22页	313K
描述
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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技术参数
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80C51GB 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.57	技术：	CMOS
uPs/uCs/外围集成电路类型：	MICROCONTROLLER	Base Number Matches：	1

80C51GB 数据手册

8XC51GB

PARALLEL I/O PORTS

Port Pins as Inputs

The 8XC51GB contains six 8-bit parallel I/O ports.

All six ports are bidirectional and consist of a latch,

an output driver, and an input buffer. Many of the

port pins have multiplexed I/O and control functions.

The pins of all six ports are configured as inputs by

writing a logic 1 to them. Since Port 0 is an open

drain port, it provides a very high input impedance.

Since pins of Port 1, 2, 3, 4 and 5 have weak pullups

(which are always on), they source a small current

when driven low externally. All ports except Port 0

have Schmitt trigger inputs.

Port Pins as Outputs

Port 0 has open drain outputs when it is not serving

as the external data bus. The internal pullup is active

only when the pin is outputting a logic 1 during exter-

nal memory access. An external pullup resistor is

required on Port 0 when it is serving as an output

port.

Port States During Reset

Ports 0 and 3 reset asynchronously to a one and

Ports 1, 2, 4, and 5 reset to a zero asynchronously.

Ports 1, 2, 3, 4, and 5 have quasi-bidirectional out-

puts. A strong pullup provides a fast rise time when

the pin is set to a logic 1. This pullup turns on for two

oscillator periods to drive the pin high and then turns

off. The pin is held high by a weak pullup.

PIN DESCRIPTIONS

The 8XC51GB will be packaged in the 68-lead PLCC

package. Its pin assignment is shown in Figure 2.

: Supply Voltage.

Writing the P0, P1, P2, P3, P4 or P5 Special Function

port registers are bit addressable.

: Circuit Ground.

Diagram is for Pin Reference Only. Package Size is Not to Scale.

272337–2

*OTP only

Figure 2. Pin Connections

1 234 5 6 7...22

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