5秒后页面跳转
捷配首页

Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> 78P2352-IGT/F
78P2352-IGT/F PDF预览

78P2352-IGT/F

更新时间： 2024-01-07 06:13:17
品牌 Logo 应用领域
TERIDIAN ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
42页 754K
描述
Dual Channel OC-3/ STM1-E/ E4 LIU

阅读下载

获取价格

78P2352-IGT/F 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：QFP
包装说明：LFQFP, QFP128,.64SQ,16针数：128
Reach Compliance Code：compliantECCN代码：5A991
HTS代码：8542.39.00.01风险等级：5.23
应用程序：SONET;SDHJESD-30 代码：S-PQFP-G128
长度：14 mm湿度敏感等级：3
功能数量：1端子数量：128
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP128,.64SQ,16封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Digital Transmission Interfaces
最大压摆率：0.35 mA标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH TRANSCEIVER
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

78P2352-IGT/F 数据手册

 浏览型号78P2352-IGT/F的Datasheet PDF文件第5页浏览型号78P2352-IGT/F的Datasheet PDF文件第6页浏览型号78P2352-IGT/F的Datasheet PDF文件第7页浏览型号78P2352-IGT/F的Datasheet PDF文件第9页浏览型号78P2352-IGT/F的Datasheet PDF文件第10页浏览型号78P2352-IGT/F的Datasheet PDF文件第11页 
78P2352  
Dual Channel  
OC-3/ STM1-E/ E4 LIU  
In SW mode only, a Full Remote (digital) Loopback  
bit FLBK is also available in the Advanced Tx  
Control register. This loopback exercises the entire  
Rx and Tx paths of the 78P2352 including the Tx  
clock recovery unit. As such, the user must enable  
either Serial Plesiochronous or Serial Loop-timing  
transmit modes to utilize the Full Remote (digital)  
Loopback.  
SERIAL CONTROL INTERFACE  
The serial port controlled registers allows a generic  
controller to interface with the 78P2352. It is used  
for mode settings, diagnostics and test, retrieval of  
status and performance information, and for on-chip  
fuse trimming during production test. The SPSL pin  
must be high in order to use the serial port.  
The serial interface consists of four pins: Serial Port  
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial  
Data In (SDI_PAR), and Serial Data Out (SDO_E4).  
EACH CHANNEL: Tx  
Lock Detect  
ECLxP/N  
Tx CDR  
TXxCKP/N  
SIxDP/N  
FIFO  
CMI  
Encoder  
SIxCKP/N  
CMIxP/N  
PIxCK  
PIx[3:0]D  
PTOxCK  
The SEN_CMI pin initiates the read and write  
operations. It can also be used to select a  
particular device allowing SCK_MON, SDI_PAR  
and SDO_E4 to be bussed together.  
SCK_MON is the clock input that times the data  
on SDI_PAR and SDO_E4. Data on SDI_PAR  
is latched in on the rising-edge of SCK_MON,  
and data on SDO_E4 is clocked out using the  
falling edge of SCK_MON.  
PMOD, SMOD[1:0], PAR  
RLBK  
SOxCKP/N  
SOxDP/N  
CMI  
Decoder  
Rx CDR  
Adaptive  
Eq.  
RXxP/N  
POx[3:0]D  
POxCK  
Lock Detect  
LOS Detect  
CMI  
LLBK  
EACH CHANNEL: Rx  
Figure 8: Remote (Digital) Loopback  
SDI_PAR is used to insert mode, address, and  
register data into the chip. Address and Data  
information are input least significant bit (LSB)  
first. The mode and address bit assignment and  
register table are shown in the following section.  
SDO_E4 is a tri-state capable output. It is used  
to output register data during a read operation.  
SDO_E4 output is normally high impedance,  
and is enabled only during the duration when  
register data is being clocked out. Read data is  
clocked out least significant bit (LSB) first.  
INTERNAL POWER-ON RESET  
Power-On Reset (POR) function is provided on chip.  
Roughly 50µs after Vcc reaches 2.4V at power up, a  
reset pulse is internally generated. This resets all  
registers to their default values as well as all state  
machines within the transceiver to known initial  
values. The reset signal is also brought out to the  
PORB pin. The PORB pin is a special function  
analog pin that allows for the following:  
•
•
•
Override the internal POR signal by driving in  
an external active low reset signal;  
If SDI_PAR coming out of the micro-controller chip is  
also tri-state capable, SDI_PAR and SDO_E4 can  
be connected together to simplify connections. The  
maximum clock frequency for register access is  
20MHz.  
PROGRAMMABLE INTERRUPTS  
In addition to the receiver LOS and LOL status pins,  
the 78P2352 provides a programmable interrupt for  
each transmitter.  
Use the internally generated POR signal to  
trigger other resets;  
Add external capacitor to slow down the  
release of power-on reset (approximately 8µs  
per nF added).  
NOTE: Do not pull-up the PORB pin to Vcc or drive  
this pin high during power-up. This will prevent the  
internal reset generator from resetting the entire chip  
and may result in errors.  
In HW control mode, the default events that trigger  
the Tx interrupt is a transmit Loss of Lock (TXLOL)  
or FIFO error (FERR).  
Page: 8 of 42  
2006 Teridian Semiconductor Corporation  
Rev. 2.4  
1...567891011...42

下载PDF

与78P2352-IGT/F相关器件

型号 品牌 描述 获取价格 数据表
78P2352-IGTR TERIDIAN Dual Channel OC-3/ STM1-E/ E4 LIU

获取价格
78P2352-IGTR/F TERIDIAN Transceiver, 2-Func, PQFP128, LEAD FREE, LQFP-128

获取价格
78P2361 PULSE T3/DS3/E3/STS-1 TRANSFORMERS

获取价格
78P2361-IH SST PCM Transceiver, 1-Func, PQCC28,

获取价格
78P2361-IP SST PCM Transceiver, 1-Func, PDIP28,

获取价格
78P2362 PULSE T3/DS3/E3/STS-1 TRANSFORMERS

获取价格

与78P2352-IGT/F相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证