Datasheet > 78P2343-IEL/A07R/F

78P2343-IEL/A07R/F

更新时间： 2024-02-21 12:45:55

品牌	Logo	应用领域
东电化 - TDK		/
页数	文件大小	规格书
37页	459K
描述
Digital Transmission Interface, E-3, PQFP100

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78P2343-IEL/A07R/F 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	QFP, QFP100,.63SQ,20	Reach Compliance Code：	compliant
风险等级：	5.22	运营商类型：	E-3
运营商类型（2）：	STS-1/OC-1	运营商类型（3）：	T-3(DS3)
JESD-30 代码：	S-PQFP-G100	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	355 mA	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

78P2343-IEL/A07R/F 数据手册

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78P2343JAT

3-port E3/DS3/STS-1 LIU

with Jitter Attenuator

Elastic Store Depth

SERIAL CONTROL INTERFACE

To optimize the trade-off between data latency and

clock wander tolerance, the FIFO elastic store depth

can be selected through the serial port by writing to

the Jitter Attenuator Control Register (JACR) as

follows:

The serial port controlled register allows a generic

controller to interface with the 78P2343JAT. It is

used for mode settings, diagnostics and test, and

the retrieval of status and performance information.

The serial interface consists of four pins: Chip Select

(CS), Serial Clock (SCK), Serial Data In (SDI), and

Serial Data Out (SDO). The CS pin initiates the

read and write operations. It can also be used to

select a particular device allowing SCK, SDI and

SDO to be bussed together. SCK is the clock input

that times the data on SDI and SDO. Data on SDI is

latched in on the rising-edge of SCK, and data on

SDO is clocked out using the falling edge of SCK.

ESP[1:0]

Elastic Store Depth

bits

Pass-Through mode

16 UI

32 UI

64 UI (default)

SDI is used to insert mode, address, and register

data into the chip. Address and Data information

are input least significant bit (LSB) first.

The Elastic Store Depth selects the nominal FIFO

read pointer address. The total or maximum elastic

store depth is set to be twice as deep as the nominal

pointer address. The circular buffer length is always

twice as long as the nominal pointer address.

SDO is a tristate capable output. It is used to output

normally high impedance, and is enabled only

during the duration when register data is being

POWER-DOWN FUNCTION

clocked out.

Read data is clocked out least

Power-down control is provided to allow the

transceivers to be shut off individually. Transmit and

receive power-down can be set independently via

the PDTX and PDRX bits in the Mode Control

set PDTX for each channel. The Serial Control

Interface and Configuration Registers are not

affected by power-down.

significant bit (LSB) first.

If SDI coming out of the micro-controller chip is also

tristate capable, SDI and SDO can be connected

together to simplify connections.

The maximum clock frequency for register access is

20MHz.

Note: To allow equipment to power up in a known

state, some register defaults are set by their

corresponding pin control at power-up.

INTERNAL POWER-ON RESET

The 78P2343JAT includes on-chip Power-On Reset

(POR) function to ensure the serial-port registers are

initialized to known default states upon power-up.

Roughly 50us after Vcc reaches 2.4V at power up,

reset is released. This reset signal also sets all state

machines within the LIU to nominal operational

states. The internal reset signal is also brought out

to the PORB pin. This pin is a multi-function pin that

allows for the following:

1) Override the internal POR signal by driving in an

external active-low reset signal;

2) Monitor the state of the internal POR signal (for

test and debug only);

3) Add external capacitor to delay the release of

the internal power-on reset signal to allow the

MSL0 pin to stabilize prior to release of reset

(approximately 8µs per nF added).

The internal resistance of the PORB pin is

approximately 5kΩ.

- 6 -

1...3 4 567 8 9...37

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与78P2343-IEL/A07R/F相关器件

型号	品牌	描述	获取价格	数据表
78P2343-IEL/F	TDK	PCM Transceiver, 1-Func, PQFP100, LEAD FREE, LQFP-100	获取价格
78P2343-IELR	TDK	PCM Transceiver, 1-Func, PQFP100, LQFP-100	获取价格
78P2343-IGT	TERIDIAN	3-port E3/DS3/STS-1 LIU with Jitter Attenuator	获取价格
78P2343-IGT	TDK	PCM Transceiver, 1-Func, PQFP100, LQFP-100	获取价格
78P2343-IGT/A07	TERIDIAN	3-port E3/DS3/STS-1 LIU with Jitter Attenuator	获取价格
78P2343-IGT/A07	TDK	Telecom IC, PQFP100	获取价格

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