Datasheet > 78P2341JAT-IGTR

78P2341JAT-IGTR

更新时间： 2024-02-21 10:28:28

品牌	Logo	应用领域
TERIDIAN		PC 电信电信集成电路
页数	文件大小	规格书
37页	407K
描述
Telecom IC,

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技术参数
数据手册

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78P2341JAT-IGTR 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.7	Is Samacsys：	N
Base Number Matches：	1

78P2341JAT-IGTR 数据手册

78P2341JAT

E3/DS3/STS-1 LIU

with Jitter Attenuator

Address Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Sub-Address

SA[1]

Bit 1

Bit 0

Read/

Write

Port Address

Assignment

PA[3]

PA[2]

PA[1]

PA[0]

SA[2]

SA[0]

R/W*

a) PA[3:0] = 0 : Global Registers

Reg.

Sub

Description

Master Control

Interrupt Control

Bit 7

Bit 6

Bit 5

Bit 4

ENDEC

<0>

Bit 3

Bit 2

Bit 1

Bit 0

Addr

Name

REGEN

<0>

INPOL

<0>

<X>

RCLKP

<0>

JAFLG

<0>

TCLKP

<0>

JAER

<0>

SRST

<0>

TXER

<1>

MSCR

DS3

<X>

(R/W)

INTC

(R/W)

RXER

<1>

RSVD

Reserved

<0>

b) PA[3:0] = 1 : Specific Registers

Reg.

Sub

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr

Name

LBO

<1>

MDCR

PDTX

<0>

PDRX

<0>

LLBK

<0>

RLBK

<0>

MON

<0>

TXEN

<1>

Mode Control

(R/W)

STAT

(R/O)

Status Monitor

Reserved

FERR

FLIM1

FLIM2

SLIP

<1>

<0>

LOS

TXNW

SGHI

<0>

SGLO

RSVD

<1>

<0>

<1>

<0>

JACR

(R/W)

Jitter Attenuator

Control

JAEN

<X>

JASL

<X>

JLBK

<0>

ESP[1]

<1>

ESP[0]

<1>

JABW

<X>

RSVD

Reserved

<0>

Note: Shaded registers in Register Table are reserved for TDK internal use only. Accessing reserved or

undefined registers may cause undesirable operation.

- 7 -

1...4 5 678 9 10...37

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