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74LVC541ADTR2G PDF预览

74LVC541ADTR2G

更新时间: 2024-10-01 01:12:11
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 104K
描述
Low-Voltage CMOS Octal Buffer Flow Through Pinout

74LVC541ADTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:compliantFactory Lead Time:1 week
风险等级:5.29系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):16 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm

74LVC541ADTR2G 数据手册

 浏览型号74LVC541ADTR2G的Datasheet PDF文件第2页浏览型号74LVC541ADTR2G的Datasheet PDF文件第3页浏览型号74LVC541ADTR2G的Datasheet PDF文件第4页浏览型号74LVC541ADTR2G的Datasheet PDF文件第5页浏览型号74LVC541ADTR2G的Datasheet PDF文件第6页浏览型号74LVC541ADTR2G的Datasheet PDF文件第7页 
74LVC541A  
Low-Voltage CMOS Octal  
Buffer Flow Through Pinout  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
www.onsemi.com  
The 74LVC541A is a high performance, non−inverting octal buffer  
operating from a 1.2 to 3.6 V supply. This device is similar in function  
to the MC74LCX244, while providing flow through architecture.  
High impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
SOIC−20 WB  
DW SUFFIX  
CASE 751D  
TSSOP−20  
DT SUFFIX  
CASE 948E  
switching noise performance. A V specification of 5.5 V allows  
I
74LVC541A inputs to be safely driven from 5 V devices. The  
74LVC541A is suitable for memory address driving and all TTL level  
bus oriented transceiver applications.  
MARKING DIAGRAMS  
Current drive capability is 24 mA at the outputs. The Output Enable  
(OE1. OE2) inputs, when HIGH, disables the output by placing them  
in a HIGH Z condition.  
20  
1
LVC541A  
AWLYYWWG  
Features  
Designed for 1.2 to 3.6 V V Operation  
CC  
5 V Tolerant − Interface Capability With 5 V TTL Logic  
Supports Live Insertion and Withdrawal  
SOIC−20 WB  
20  
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
24 mA Output Sink and Source Capability  
LVC  
541A  
ALYW G  
G
Near Zero Static Supply Current in All Three Logic States (10 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 250 mA  
1
ESD Performance:  
TSSOP−20  
Human Body Model > 2000 V  
Machine Model > 200 V  
A
= Assembly Location  
L, WL = Wafer Lot  
Y, YY = Year  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
W, WW = Work Week  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
December, 2015 − Rev. 0  
74LVC541A/D  

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