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74LVC2952AD,118 PDF预览

74LVC2952AD,118

更新时间: 2024-10-01 15:44:31
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
19页 108K
描述
74LVC2952A - Octal registered transceiver with 5 V tolerant inputs/outputs; 3-state SOP 24-Pin

74LVC2952AD,118 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOP针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):8.6 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74LVC2952AD,118 数据手册

 浏览型号74LVC2952AD,118的Datasheet PDF文件第2页浏览型号74LVC2952AD,118的Datasheet PDF文件第3页浏览型号74LVC2952AD,118的Datasheet PDF文件第4页浏览型号74LVC2952AD,118的Datasheet PDF文件第5页浏览型号74LVC2952AD,118的Datasheet PDF文件第6页浏览型号74LVC2952AD,118的Datasheet PDF文件第7页 
74LVC2952A  
Octal registered transceiver with 5 V tolerant inputs/outputs;  
3-state  
Rev. 02 — 29 June 2004  
Product data sheet  
1. General description  
The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device  
superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can  
handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V  
and 5 V environment.  
The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back-to-back  
registers store data flowing in both directions between two bidirectional buses. Data  
applied to the inputs is entered and stored on the rising edge of the clock (CPAB, CPBA)  
provided that the clock enable (CEAB, CEBA) input is LOW. The data is then present at  
the 3-state output buffers, but is only accessible when the output enable (OEAB, OEBA)  
input is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.  
2. Features  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Inputs accept voltages up to 5.5 V  
Flow-through pin-out architecture  
Complies with JEDEC standard JESD8-B/JESD36  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C.  
 
 

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