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74LVC162244ADL,118 PDF预览

74LVC162244ADL,118

更新时间： 2024-01-05 23:07:04
品牌 Logo 应用领域
恩智浦 - NXP PC驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 92K
描述
74LVC162244A; 74LVCH162244A - 16-bit buffer/line driver SSOP 48-Pin

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74LVC162244ADL,118 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：SSOP包装说明：SSOP, SSOP48,.4
针数：48Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：7.56
控制类型：ENABLE LOW系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：15.875 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：7.5 ns
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
座面最大高度：2.8 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
Base Number Matches：1

74LVC162244ADL,118 数据手册

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Philips Semiconductors  
Product specification  
16-bit buffer/line driver, 30 Ω series termination  
resistors; 5 V tolerant input/output; 3-state  
74LVC162244A;  
74LVCH162244A  
FEATURES  
DESCRIPTION  
• 5 V tolerant inputs/outputs for interfacing with 5 V logic  
• Wide supply voltage range from 1.2 to 3.6 V  
• CMOS low power consumption  
The 74LVC(H)162244A is a high-performance, low power,  
low voltage, Si-gate CMOS device, superior to most  
advanced CMOS compatible TTL families. Inputs can be  
driven from either 3.3 or 5 V devices. In 3-state operation,  
outputs can handle 5 V. These features allow the use of  
these devices as a mixed 3.3 and 5 V environment.  
• MULTIBYTE flow-through standard pin-out architecture  
• Low inductance multiple power and ground pins for  
minimum noise and ground bounce  
The 74LVC(H)162244A is a 16-bit non-inverting buffer/line  
driver with 3-state outputs. The device can be used as four  
4-bit buffers, two 8-bit buffers or one 16-bit buffer. The  
3-state outputs are controlled by the output enable inputs  
1OE, 2OE, 3OE and 4OE. A HIGH on nOE causes the  
outputs to assume a high-impedance OFF-state.  
• Direct interface with TTL levels  
• Inputs accept voltages up to 5.5 V  
• Integrated 30 Ω termination resistors  
• All data inputs have bushold (74LVCH162244A only)  
• Complies with JEDEC standard no. 8-1A  
The 74LVCH162244A bushold data inputs eliminates the  
need for external termination resistors to hold unused  
inputs.  
• ESD protection:  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
The 74LVC(H)162244A is designed with 30 Ω series  
termination resistors in both HIGH and LOW output stages  
to reduce line noise.  
• Specified from −40 to +85 °C and −40 to +125 °C.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.  
SYMBOL  
PARAMETER  
CONDITIONS  
CL = 50 pF; VCC = 3.3 V  
CL = 50 pF; VCC = 3.3 V  
TYPICAL  
3.0  
UNIT  
tPHL/tPLH  
tPZH/tPZL  
tPHZ/tPLZ  
CI  
propagation delay nAn to nYn  
3-state output enable time nOE to nYn  
ns  
ns  
ns  
pF  
3.5  
2.8  
5.0  
3-state output disable time nOE to nYn CL = 50 pF; VCC = 3.3 V  
input capacitance  
CPD  
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2  
outputs enabled  
outputs disabled  
12  
pF  
pF  
4.0  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = total load switching outputs;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
2. The condition is VI = GND to VCC  
.
2003 Dec 12  
2
 
 
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中文翻译

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74LVC162244ADL,118 替代型号

型号 品牌 替代类型 描述 数据表
74LVC162244ADL NXP

完全替代

 16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolera
SN74LVCH162244ADLR TI

类似代替

 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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