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74LVC162245ADGG PDF预览

74LVC162245ADGG

更新时间： 2023-09-03 20:31:09
品牌 Logo 应用领域
安世 - NEXPERIA PC光电二极管逻辑集成电路
页数 文件大小 规格书
14页 252K
描述
16-bit transceiver with direction pin; 30 Ω series termination resistors; 5 V tolerant input/output; 3-stateProduction

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74LVC162245ADGG 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP48,.3,20Reach Compliance Code：unknown
风险等级：5.68Is Samacsys：N
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
JESD-30 代码：R-PDSO-G48最大I（ol）：0.012 A
位数：8功能数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 VProp。Delay @ Nom-Sup：6.3 ns
认证状态：Not Qualified子类别：Bus Driver/Transceivers
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUALBase Number Matches：1

74LVC162245ADGG 数据手册

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74LVC162245A; 74LVCH162245A  
16-bit transceiver with direction pin; 30 Ω series termination  
resistors; 5 V tolerant input/output; 3-state  
Rev. 8 — 23 September 2021  
Product data sheet  
1. General description  
The 74LVC162245A; 74LVCH162245A is a 16-bit transceiver with 30 Ω termination resistors and  
3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The  
device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/  
receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume  
a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature  
allows the use of these devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
The 74LVCH162245A bus hold on data inputs eliminates the need for external pull-up resistors to  
hold unused inputs.  
2. Features and benefits  
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Overvoltage tolerant inputs to 5.5 V  
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Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground bounce  
Direct interface with TTL levels  
Integrated 30 Ω termination resistors  
IOFF circuitry provides partial Power-down mode operation  
All data inputs have bus hold (74LVCH162245A only)  
Complies with JEDEC standard:  
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•
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JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
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ESD protection:  
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HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
 
 
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