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74LV161284DGGRE4 PDF预览

74LV161284DGGRE4

更新时间: 2024-01-28 12:25:18
品牌 Logo 应用领域
德州仪器 - TI 驱动器接口集成电路光电二极管
页数 文件大小 规格书
11页 185K
描述
19-BIT BUS INTERFACE

74LV161284DGGRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-48针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:N差分输出:NO
驱动器位数:13输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE 1284
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm湿度敏感等级:1
功能数量:13端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大接收延迟:30 ns接收器位数:17
座面最大高度:1.2 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:30 ns
宽度:6.1 mmBase Number Matches:1

74LV161284DGGRE4 数据手册

 浏览型号74LV161284DGGRE4的Datasheet PDF文件第1页浏览型号74LV161284DGGRE4的Datasheet PDF文件第3页浏览型号74LV161284DGGRE4的Datasheet PDF文件第4页浏览型号74LV161284DGGRE4的Datasheet PDF文件第5页浏览型号74LV161284DGGRE4的Datasheet PDF文件第6页浏览型号74LV161284DGGRE4的Datasheet PDF文件第7页 
SN74LV161284  
19-BIT BUS INTERFACE  
SCLS426C OCTOBER 1998 REVISED NOVEMBER 2002  
FUNCTION TABLE  
INPUTS  
OUTPUT  
MODE  
HD  
DIR  
L
Open drain  
Totem pole  
Totem pole  
Open drain  
Totem pole  
Totem pole  
A9A13 to Y9Y13 and PERI LOGIC IN to PERI LOGIC OUT  
L
B1B8 to A1A8 and C14C17 to A14A17  
L
H
B1B8 to A1A8, A9A13 to Y9Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14C17 to A14A17  
A1A8 to B1B8, A9A13 to Y9Y13, and PERI LOGIC IN to PERI LOGIC OUT  
C14C17 to A14A17  
H
L
H
H
A1A8 to B1B8, A9A13 to Y9Y13, C14C17 to A14A17, and PERI LOGIC IN to PERI LOGIC OUT  
logic diagram (positive logic)  
42  
V
CC  
CABLE  
DIR  
See Note B  
48  
1
See Note B  
HD  
See Note A  
A1A8  
B1B8  
A9A13  
Y9Y13  
19  
30  
PERI LOGIC IN  
PERI LOGIC OUT  
A14A17  
C14C17  
24  
25  
HOST LOGIC OUT  
HOST LOGIC IN  
NOTES: A. The PMOS prevents backdriving current from the signal pins to V  
CABLE when V  
CABLE when V  
CABLE is open or at GND.  
CABLE is open or at GND. The PMOS  
CC  
CC  
CC  
CC  
B. The PMOS prevents backdriving current from the signal pins to V  
is turned off when the associated driver is in the low state.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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