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74LS374DCQR PDF预览

74LS374DCQR

更新时间： 2024-11-06 13:02:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器
页数 文件大小 规格书
8页 91K
描述
Bus Driver, 8-Func, TTL, CDIP20,

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中文翻译

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74LS374DCQR 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete包装说明：DIP, DIP20,.3
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.22Is Samacsys：N
JESD-30 代码：R-XDIP-T20JESD-609代码：e0
逻辑集成电路类型：BUS DRIVER功能数量：8
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V子类别：FF/Latches
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
Base Number Matches：1

74LS374DCQR 数据手册

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April 1986  
Revised March 2000  
DM74LS373 • DM74LS374  
3-STATE Octal D-Type Transparent Latches  
and Edge-Triggered Flip-Flops  
General Description  
Features  
■ Choice of 8 latches or 8 D-type flip-flops in a single  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
package  
■ 3-STATE bus-driving outputs  
■ Full parallel-access for loading  
■ Buffered control inputs  
■ P-N-P inputs reduce D-C loading on data lines  
The eight latches of the DM74LS373 are transparent D-  
type latches meaning that while the enable (G) is HIGH the  
Q outputs will follow the data (D) inputs. When the enable  
is taken LOW the output will be latched at the level of the  
data that was set up.  
The eight flip-flops of the DM74LS374 are edge-triggered  
D-type flip flops. On the positive transition of the clock, the  
Q outputs will be set to the logic states that were set up at  
the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the latches or flip-flops. That is, the old data can be  
retained or new data can be entered even while the outputs  
are OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS373WM  
DM74LS373SJ  
DM74LS373N  
DM74LS374WM  
DM74LS374SJ  
IDM29901NC  
M20B  
M20D  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006431  
www.fairchildsemi.com  
12345678

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74LS374FC FAIRCHILD

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74LS374FCQM ROCHESTER

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 		Bus Driver,
74LS374FCQR ROCHESTER

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 		Bus Driver,
74LS374PC FAIRCHILD

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 		D Flip-Flop, LS Series, 1-Func, High Level Triggered, 8-Bit, Complementary Output, TTL, PD
74LS374PCQM FAIRCHILD

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 		Bus Driver, 8-Func, TTL, PDIP20,
74LS374PCQM ROCHESTER

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 		Bus Driver,
74LS375DC ETC

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 		4-Bit D-Type Latch
74LS375DCQM FAIRCHILD

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 		D Latch, 1-Func, 4-Bit, TTL, CDIP16,
74LS375DCQR FAIRCHILD

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 		D Latch, 1-Func, 4-Bit, TTL, CDIP16,
74LS375FCQM FAIRCHILD

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 		D Latch, 1-Func, 4-Bit, TTL, CDFP16,

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