Datasheet > 74HCT4059N,112

74HCT4059N,112

更新时间： 2024-02-21 18:34:11

品牌	Logo	应用领域
恩智浦 - NXP		输入元件光电二极管逻辑集成电路触发器
页数	文件大小	规格书
20页	132K
描述
74HC(T)4059 - Programmable divide-by-n counter DIP 24-Pin

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74HCT4059N,112 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP24,.6
针数：	24	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	8.53
其他特性：	PROGRAMMABLE TO DIVIDE INPUT BY 3-15999; 10 MODES OF OPERATION; SCHMITT TRIGGER ON CLOCK INPUT	计数方向：	DOWN
系列：	HCT	JESD-30 代码：	R-PDIP-T24
JESD-609代码：	e3	长度：	31.7 mm
负载电容（CL）：	50 pF	负载/预设输入：	YES
逻辑集成电路类型：	DIVIDE BY N COUNTER	最大频率@ Nom-Sup：	17000000 Hz
工作模式：	ASYNCHRONOUS	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP24,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	260	电源：	5 V
传播延迟（tpd）：	69 ns	认证状态：	Not Qualified
座面最大高度：	5.1 mm	子类别：	Prescaler/Multivibrators
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	TIN	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	触发器类型：	POSITIVE EDGE
宽度：	15.24 mm	最小 fmax：	40 MHz
Base Number Matches：	1

74HCT4059N,112 数据手册

Philips Semiconductors

Product speciﬁcation

Programmable divide-by-n counter

74HC/HCT4059

If n = 8 479 and the selected mode = 10, the preset

value = 8 479/10 with a remainder of 9, thus the JAM

inputs must be set as shown in Table 3.

Control inputs K_band K_ccan be used to initiate and lock

the counter in the “master preset” mode. In this condition

the flip-flops in the counter are preset in accordance with

the JAM inputs and the counter remains in that mode as

long as K_band K_cboth remain LOW. The counter begins

to count down from the preset state when a counting mode

other than the “master preset” mode is selected.

Whenever the “master preset” mode is used, control

signals K_b= K_c= LOW must be applied for at least 2 full

clock pulses. After the “master preset” mode inputs have

been changed to one of the counting modes, the next

positive-going clock transition changes an internal flip-flop

so that the count-down begins on the second

To verify:

n = 10 (1 000 × 0 + 100 × 8 + 10 × 4 + 1 × 7) + 9

n = 8 479.

The three decades of the intermediate counting section

can be preset to a binary 15 instead of a BCD 9. In this

case the first cycle of a counter consists of 15 count

pulses, the next cycles consisting of 10 counting pulses.

Thus the place value of the three decades are still 1, 10

and 100. For example, in the divide-by-8 mode, the

number from which the intermediate counting section

begins to count-down can be preset to:

positive-going clock transition. Thus, after a “master

preset” mode, there is always one extra count before the

output goes HIGH. Figure 6 illustrates the operation of the

counter in the divide-by-8 mode starting from the preset

state 3.

3rd decade: 1 500

2nd decade: 150

1st decade:

If the “master preset” mode is started two clock cycles or

less before an output pulse, the output pulse will appear at

the correct moment. When the output pulse appears and

the “master preset” mode is not selected, the counter is

preset according to the states of the JAM inputs.

The last counting section can be preset to a maximum of

1, with a place value of 1 000. The first counting section

can be preset to a maximum of 7. To calculate n:

n = 8 (1 000 × 1 + 100 × 15 + 10 × 15 + 1 × 15) + 7

When K_a, K_b, K_cand LE are LOW, the counter operates in

the “preset inhibit” mode, during which the counter divides

at a fixed rate of 10 000, independent of the state of the

JAM inputs. However, the first cycle length after leaving

the “master preset” mode is determined by the JAM inputs.

n = 21 327.

21 327 is the maximum possible count in the divide-by-8

mode. The highest count of the various modes is shown in

the Function table, in the column entitled “binary counter

range”.

When K_a, K_band K_care LOW and input LE = HIGH, the

counter operates in the normal divide-by-10 mode,

however, without the latch operation at the output.

The mode select inputs permit, when used with decimal

programming, a non-BCD least significant digit. For

example, the channel spacing in a radio is 12.5 kHz, it may

be convenient to program the counter in decimal steps of

100 kHz subdivided into 8 steps of 12.5 kHz controlled by

the least significant digit. Also frequency synthesizer

channel separations of 10, 12.5, 20, 25 and 50 parts can

be chosen by the mode select inputs. This is called

“Fractional extension”. A similar extension called “Half

channel offset” can be obtained in modes 2, 4, 6 and 8, if

the JAM inputs are switched between zero and 1, 2, 3 and

4 respectfully. This is illustrated in Fig.5.

This device is particularly advantageous in digital

frequency synthesizer circuits (VHF, UHF, FM, AM etc.)

for communication systems, where programmable

divide-by-”n” counters are an integral part of the

synthesizer phase-locked-loop sub-system. The

74HC/HCT4059 can also be used to perform the

synthesizer “fixed divide-by-n” counting function, as well

as general purpose counting for instrumentation functions

such as totalizers, production counters and “time out”

timers.

This feature is used primarily in cases where radio

channels are allocated according to the following formula:

Schmitt-trigger action at the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

Channel frequency = channel spacing x (N + 0.5)

N is an integer.

1998 Jul 08

1 234 5 6 7...20

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