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74HC58N,652 PDF预览

74HC58N,652

更新时间: 2024-01-25 12:53:52
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
5页 35K
描述
74HC58 - Dual AND-OR gate DIP 14-Pin

74HC58N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:8.59
其他特性:ASYMMETRICAL I/P'S系列:HC/UH
JESD-30 代码:R-PDIP-T14JESD-609代码:e4
长度:19.025 mm负载电容(CL):50 pF
逻辑集成电路类型:AND-OR GATE最大I(ol):0.004 A
功能数量:2输入次数:6
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:29 ns传播延迟(tpd):35 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:4.2 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.62 mm
Base Number Matches:1

74HC58N,652 数据手册

 浏览型号74HC58N,652的Datasheet PDF文件第1页浏览型号74HC58N,652的Datasheet PDF文件第3页浏览型号74HC58N,652的Datasheet PDF文件第4页浏览型号74HC58N,652的Datasheet PDF文件第5页 
Philips Semiconductors  
Product specification  
Dual AND-OR gate  
74HC58  
FEATURES  
Output capability: standard  
ICC category: SSI  
GENERAL DESCRIPTION  
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).  
It is specified in compliance with JEDEC standard no. 7A.  
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and  
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PHL/ tPLH  
PARAMETER  
propagation delay  
CONDITIONS  
UNIT  
HC  
t
CL = 15 pF; VCC = 5 V  
1n to 1Y  
11  
9
ns  
ns  
pF  
2n to 2Y  
CI  
input capacitance  
3.5  
CPD  
power dissipation capacitance per  
gate  
notes 1 and 2  
18  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in V  
(CL × VCC2 × fo) = sum of outputs  
2. For HC the condition is VI = GND to VCC  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2

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