74HC563N

更新时间： 2024-02-29 18:44:11

品牌	Logo	应用领域
恩智浦 - NXP		总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数	文件大小	规格书
7页	67K
描述
Octal D-type transparent latch; 3-state; inverting

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74HC563N 技术参数

生命周期：	Active	包装说明：	TSSOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.36	其他特性：	BROADSIDE VERSION OF 533
系列：	HC/UH	JESD-30 代码：	R-PDSO-G20
长度：	6.5 mm	负载电容（CL）：	50 pF
逻辑集成电路类型：	BUS DRIVER	位数：	8
功能数量：	1	端口数量：	2
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
输出极性：	INVERTED	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	传播延迟（tpd）：	44 ns
认证状态：	Not Qualified	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
Base Number Matches：	1

74HC563N 数据手册

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

TTL (LSTTL). They are specified in

common to all latches.

FEATURES

compliance with JEDEC standard no.

7A.

When LE is HIGH, data at the D_n

inputs enter the latches. In this

condition the latches are transparent,

i.e. a latch output will change state

each time its corresponding D-input

changes.

• 3-state inverting outputs for bus

oriented applications

The 74HC/HCT563 are octal D-type

transparent latches featuring

separate D-type inputs for each latch

and inverting 3-state outputs for bus

oriented applications.

A latch enable (LE) input and an

output enable (OE) input are common

to all latches.

• Inputs and outputs on opposite

sides of package allowing easy

interface with microprocessor

• Common 3-state output enable

input

When LE is LOW the latches store the

information that was present at the

D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE.

• Output capability: bus driver

• I_CCcategory: MSI

When OE is LOW, the contents of the

8 latches are available at the outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the latches.

The “563” is functionally identical to

the “573”, but has inverted outputs.

GENERAL DESCRIPTION

The “563” consists of eight D-type

transparent latches with 3-state

inverting outputs. The LE and OE are

The 74HC/HCT563 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

UNIT

SYMBOL

PARAMETER

CONDITIONS

HCT

t_PHL/t_PLH

C_I

propagation delay D_n, LE to Q_n

input capacitance

C_L= 15 pF; V_CC= 5 V

notes 1 and 2

3.5

C_PD

power dissipation capacitance per latch

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

for HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

123 4 5 6 7

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与74HC563N相关器件

型号	品牌	描述	获取价格	数据表
74HC563NB	NXP	IC HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20, Bus Driver/Transceiver	获取价格
74HC563PW	NXP	Octal D-type transparent latch; 3-state; inverting	获取价格
74HC563PW-T	NXP	IC HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, Bus Driver/Transceiver	获取价格
74HC563U	NXP	IC HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, UUC, DIE, Bus Driver/Transceiver	获取价格
74HC564	NXP	Octal D-type flip-flop; positive-edge trigger; 3-state; inverting	获取价格
74HC564D	NXP	Octal D-type flip-flop; positive-edge trigger; 3-state; inverting	获取价格

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