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74HC4059PW-T

更新时间： 2024-01-30 01:47:23

品牌	Logo	应用领域
恩智浦 - NXP		计数器
页数	文件大小	规格书
20页	151K
描述
IC HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PDSO24, Counter

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技术参数
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74HC4059PW-T 技术参数

生命周期：	Obsolete	包装说明：	TSSOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	Is Samacsys：	N
其他特性：	PROGRAMMABLE TO DIVIDE INPUT BY 3-15999; 10 MODES OF OPERATION; SCHMITT TRIGGER ON CLOCK INPUT	计数方向：	DOWN
系列：	HC/UH	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	负载/预设输入：	YES
逻辑集成电路类型：	DIVIDE BY N COUNTER	工作模式：	ASYNCHRONOUS
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：	300 ns	认证状态：	Not Qualified
座面最大高度：	1.1 mm	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	4.4 mm	最小 fmax：	40 MHz
Base Number Matches：	1

74HC4059PW-T 数据手册

Philips Semiconductors

Product speciﬁcation

Programmable divide-by-n counter

74HC/HCT4059

In the divide-by-n mode, a clock cycle wide pulse is

generated with a frequency rate equal to the input

frequency divided by n.

FEATURES

• Synchronous programmable divide-by-n counter

• Presettable down counter

The function of the mode select and JAM inputs are

illustrated in the following examples. In the divide-by-2

mode, only one flip-flop is needed in the first counting

section. Therefore the last (5th) counting section has three

flip-flops that can be preset to a maximum count of seven

with a place value of thousands. This counting mode is

selected when K_ato K_care set HIGH. In this case input J₁

is used to preset the first counting section and J₂to J₄are

used to preset the last (5th) counting section.

• Fully static operation

• Mode select control of initial decade counting function

(divide-by-10, 8, 5, 4 and 2)

• Master preset initialization

• Latchable output

• Easily cascadable with other counters

• Four operating modes:

timer

divider-by-n

divide-by-10 000

master preset

If the divide-by-10 mode is desired for the first section, K_a

and K_bare set HIGH and K_cis set LOW. The JAM inputs

J₁to J₄are used to preset the first counting section (there

is no last counting section). The intermediate counting

section consists of three cascaded BCD decade

(divide-by-10) counters, presettable by means of the JAM

inputs J₅to J₁₆.

• Output capability: standard

• I_CCcategory: MSI

The preset of the counter to a desired divide-by-n is

achieved as follows:

GENERAL DESCRIPTION

The 74HC/HCT4059 are high-speed Si-gate CMOS

devices and are pin compatible with the “4059” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

n = (MODE⁽¹⁾) (1 000 x decade 5 preset

+ 100 x decade 4 preset

+ 10 x decade 3 preset

+ 1 x decade 2 preset)

The 74HC/HCT4059 are divide-by-n counters which can

be programmed to divide an input frequency by any

number (n) from 3 to 15 999. There are four operating

modes, timer, divide-by-n, divide-by-10 000 and master

preset, which are defined by the mode select inputs (K_ato

K_c) and the latch enable input (LE) as shown in the

Function table.

+ decade 1 preset

To calculate preset values for any “n” count, divide the “n”

count by the selected mode. The resultant is the

corresponding preset value of the 5th to the 2nd decade

with the remainder being equal to the 1st decade value;

preset value = n/mode.

If n = 8 479, and the selected mode = 5, the preset

value = 8 479/5 = 1 695 with a remainder of 4, thus the

JAM inputs must be set as shown in Table 1.

The complete counter consists of a first counting stage, an

intermediate counting stage and a fifth counting stage. The

first counter stage consists of four independent flip-flops.

Depending on the divide-by-mode, at least one flip-flop is

placed at the input of the intermediate stage (the remaining

flip-flops are placed at the fifth stage with a place value of

thousands). The intermediate stage consists of three

cascaded decade counters, each containing four flip-flops.

To verify the results, use the given equation:

n = 5 (1 000 × 1 + 100 × 6 + 10 × 9 + 1 × 5) + 4

n = 8 479.

If n = 12 382 and the selected mode = 8, the preset

value = 12 382/8 = 1 547 with a remainder of 6, thus the

JAM inputs must be set as shown in Table 2.

All flip-flops can be preset to a desired state by means of

the JAM inputs (J₁to J₁₆), during which the clock input

(CP) will cause all stages to count from n to zero. The

zero-detect circuit will then cause all stages to return to the

JAM count, during which an output pulse is generated. In

the timer mode, after an output pulse is generated, the

output pulse remains HIGH until the latch input (LE) goes

LOW. The counter will advance, even if LE is HIGH and

the output is latched in the HIGH state.

To verify:

n = 8 (1 000 × 1 + 100 × 5 + 10 × 4 + 1 × 7) + 6

n = 12 382.

(1) MODE = first counting section divider

(10, 8, 5, 4 or 2).

1998 Jul 08

123 4 5 6 7...20

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