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74HC194D PDF预览

74HC194D

更新时间： 2024-01-04 23:49:12
品牌 Logo 应用领域
恩智浦 - NXP 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 83K
描述
4-bit bidirectional universal shift register

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74HC194D 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.44其他特性：HOLD MODE
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDIP-T16JESD-609代码：e3/e4
长度：19.025 mm负载电容（CL）：50 pF
逻辑集成电路类型：PARALLEL IN PARALLEL OUT位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：44 ns
认证状态：Not Qualified座面最大高度：4.2 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：AUTOMOTIVE
端子面层：TIN/NICKEL PALLADIUM GOLD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：20 MHzBase Number Matches：1

74HC194D 数据手册

 浏览型号74HC194D的Datasheet PDF文件第1页浏览型号74HC194D的Datasheet PDF文件第3页浏览型号74HC194D的Datasheet PDF文件第4页浏览型号74HC194D的Datasheet PDF文件第5页浏览型号74HC194D的Datasheet PDF文件第6页浏览型号74HC194D的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
4-bit bidirectional universal shift register  
74HC/HCT194  
and shifted from left to right (Q0 → Q1 → Q2, etc.) or, right  
to left (Q3 → Q2 → Q1, etc.) or parallel data can be  
entered, loading all 4 bits of the register simultaneously.  
When both S0 and S1 are LOW, existing data is retained in  
a hold (“do nothing”) mode. The first and last stages  
provide D-type serial data inputs (DSR, DSL) to allow  
multistage shift right or shift left data transfers without  
interfering with parallel load operation.  
FEATURES  
• Shift-left and shift-right capability  
• Synchronous parallel and serial data transfer  
• Easily expanded for both serial and parallel operation  
• Asynchronous master reset  
• Hold (“do nothing”) mode  
• Output capability: standard  
Mode select and data inputs are edge-triggered,  
responding only to the LOW-to-HIGH transition of the  
clock (CP). Therefore, the only timing restriction is that the  
mode control and selected data inputs must be stable one  
set-up time prior to the positive transition of the clock  
pulse.  
• ICC category: MSI  
GENERAL DESCRIPTION  
The 74HC/HCT194 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The four parallel data inputs (D0 to D3) are D-type inputs.  
Data appearing on the D0 to D3 inputs, when S0 and S1 are  
HIGH, is transferred to the Q0 to Q3 outputs respectively,  
following the next LOW-to-HIGH transition of the clock.  
When LOW, the asynchronous master reset (MR)  
overrides all other input conditions and forces the Q  
outputs LOW.  
The functional characteristics of the 74HC/HCT194 4-bit  
bidirectional universal shift registers are indicated in the  
logic diagram and function table. The registers are fully  
synchronous.  
The “194” design has special features which increase the  
range of application. The synchronous operation of the  
device is determined by the mode select inputs (S0, S1).  
As shown in the mode select table, data can be entered  
The “194” is similar in operation to the “195” universal shift  
register, with added features of shift-left without external  
connections and hold (“do nothing”) modes of operation.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PHL/ tPLH  
PARAMETER  
CONDITIONS  
UNIT  
HC  
HCT  
t
propagation delay  
CL = 15 pF; VCC = 5 V  
CP to Qn  
14  
11  
15  
ns  
tPHL  
fmax  
CI  
MR to Qn  
15  
77  
3.5  
40  
ns  
maximum clock frequency  
input capacitance  
102  
3.5  
40  
MHz  
pF  
CPD  
power dissipation capacitance per package  
notes 1 and 2  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
∑ = (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V  
December 1990  
2
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