Datasheet > 74HC191DB,118

74HC191DB,118

更新时间： 2024-01-24 02:56:53

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管输出元件逻辑集成电路触发器
页数	文件大小	规格书
14页	102K
描述
74HC(T)191 - Presettable synchronous 4-bit binary up/down counter SSOP1 16-Pin

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74HC191DB,118 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	SSOP1	包装说明：	SSOP,
针数：	16	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.34
Is Samacsys：	N	其他特性：	TCO OUTPUT
计数方向：	BIDIRECTIONAL	系列：	HC/UH
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	6.2 mm	负载电容（CL）：	50 pF
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	湿度敏感等级：	1
位数：	4	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	66 ns	认证状态：	Not Qualified
座面最大高度：	2 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
触发器类型：	POSITIVE EDGE	宽度：	5.3 mm
最小 fmax：	13 MHz	Base Number Matches：	1

74HC191DB,118 数据手册

Philips Semiconductors

Product speciﬁcation

Presettable synchronous 4-bit binary

up/down counter

74HC/HCT191

Overflow/underflow indications are provided by two types

of outputs, the terminal count (TC) and ripple clock (RC).

The TC output is normally LOW and goes HIGH when a

circuit reaches zero in the count-down mode or reaches

“15” in the count-up-mode. The TC output will remain

HIGH until a state change occurs, either by counting or

presetting, or until U/D is changed. Do not use the TC

output as a clock signal because it is subject to decoding

spikes. The TC signal is used internally to enable the

RC output. When TC is HIGH and CE is LOW, the RC

output follows the clock pulse (CP). This feature simplifies

the design of multistage counters as shown in Figs 5

and 6.

FEATURES

• Synchronous reversible counting

• Asynchronous parallel load

• Count enable control for synchronous expansion

• Single up/down control input

• Output capability: standard

• I_CCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT191 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

In Fig.5, each RC output is used as the clock input to the

next higher stage. It is only necessary to inhibit the first

stage to prevent counting in all stages, since a HIGH on

CE inhibits the RC output pulse as indicated in the function

table. The timing skew between state changes in the first

and last stages is represented by the cumulative delay of

the clock as it ripples through the preceding stages. This

can be a disadvantage of this configuration in some

applications.

The 74HC/HCT191 are asynchronously presettable 4-bit

binary up/down counters. They contain four master/slave

flip-flops with internal gating and steering logic to provide

asynchronous preset and synchronous count-up and

count-down operation.

Asynchronous parallel load capability permits the counter

to be preset to any desired number. Information present on

the parallel data inputs (D₀to D₃) is loaded into the counter

and appears on the outputs when the parallel load (PL)

input is LOW. As indicated in the function table, this

operation overrides the counting function.

Fig.6 shows a method of causing state changes to occur

simultaneously in all stages. The RC outputs propagate

the carry/borrow signals in ripple fashion and all clock

inputs are driven in parallel. In this configuration the

duration of the clock LOW state must be long enough to

allow the negative-going edge of the carry/borrow signal to

ripple through to the last stage before the clock goes

HIGH. Since the RC output of any package goes HIGH

shortly after its CP input goes HIGH there is no such

restriction on the HIGH-state duration of the clock.

Counting is inhibited by a HIGH level on the count enable

(CE) input. When CE is LOW internal state changes are

initiated synchronously by the LOW-to-HIGH transition of

the clock input. The up/down (U/D) input signal determines

the direction of counting as indicated in the function table.

The CE input may go LOW when the clock is in either

state, however, the LOW-to-HIGH CE transition must

occur only when the clock is HIGH. Also, the U/D input

should be changed only when either CE or CP is HIGH.

In Fig.7, the configuration shown avoids ripple delays and

their associated restrictions. Combining the TC signals

from all the preceding stages forms the CE input for a

given stage. An enable must be included in each carry

gate in order to inhibit counting. The TC output of a given

stage it not affected by its own CE signal therefore the

simple inhibit scheme of Figs 5 and 6 does not apply.

December 1990

123 4 5 6 7...14

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与74HC191DB,118相关器件

型号	品牌	描述	获取价格	数据表
74HC191DB-T	NXP	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, S	获取价格
74HC191D-T	ETC	Synchronous Up/Down Counter	获取价格
74HC191N	NXP	Presettable synchronous 4-bit binary up/down counter	获取价格
74HC191N,652	NXP	74HC(T)191 - Presettable synchronous 4-bit binary up/down counter DIP 16-Pin	获取价格
74HC191N-B	PHILIPS	Binary Counter, Synchronous, Bidirectional, CMOS, PDIP16	获取价格
74HC191PW	NXP	Presettable synchronous 4-bit binary up/down counter	获取价格

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