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74FCT388915T133J PDF预览

74FCT388915T133J

更新时间： 2024-02-02 10:20:53
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路输出元件
页数 文件大小 规格书
10页 154K
描述
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

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中文翻译

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74FCT388915T133J 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73系列：FCT
输入调节：MUXJESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：10.2 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：1
端子数量：28实输出次数：7
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：240
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.35 ns
座面最大高度：2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：5.3 mm最小 fmax：133 MHz
Base Number Matches：1

74FCT388915T133J 数据手册

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IDT74FCT388915T  
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)  
COMMERCIALTEMPERATURERANGE  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
tRISE/FALL  
AllOutputs  
Parameter  
Condition(1)  
Min.  
0.2(2)  
Max.  
Unit  
Rise/FallTime  
Load = 50Ω to VCC/2, CL = 20pF  
2
ns  
(between0.8Vand2V)  
OutputPulseWidth  
Q, Q, Q/2 outputs(3) Q0-Q4, Q5, Q/2, @ 1.5V  
(3)  
tPULSEWIDTH  
Load = 50Ω to VCC/2, CL = 20pF  
0.5tCYCLE–0.8(5) 0.5tCYCLE+0.8(5)  
0.5tCYCLE–1(5) 0.5tCYCLE+1(5)  
ns  
ns  
ns  
ps  
ps  
ps  
ms  
tPULSEWIDTH  
2QOutput(3)  
tPD  
OutputPulseWidth  
2Q @ 1.5V  
SYNC input to FEEDBACK delay  
Load = 50Ω to VCC/2, CL = 20pF  
+0.1  
—
+1.3  
600  
250  
800  
10  
(3)  
(5)  
SYNC-FEEDBACK (measured at SYNC0 or 1 and FEEDBACK input pins) 0.1µF from LF to Analog GND  
tSKEWr  
(3,4)  
OutputtoOutputSkewbetweenoutputs 2Q,Q0-Q4,  
Q/2(risingedges only)  
Load = 50Ω to VCC/2, CL = 20pF  
(rising)  
tSKEWf  
OutputtoOutputSkew  
—
(3,4)  
(falling)  
betweenoutputsQ0-Q4(fallingedgesonly)  
OutputtoOutputSkew  
tSKEWall(3,4)  
—
2Q, Q/2, Q0-Q4 rising, Q5 falling  
TimerequiredtoacquirePhase-Lockfromtime  
SYNC input signal is received  
OutputEnableTime  
(6)  
(2)  
tLOCK  
1
(2)  
tPZH  
tPZL  
tPHZ  
tPLZ  
3
14  
14  
ns  
ns  
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q  
OutputDisableTime  
(2)  
3
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q  
GENERAL AC SPECIFICATION NOTES:  
1. See test circuit and waveforms.  
2. Minimum limits are guaranteed but not tested.  
3. These specifications are guaranteed but not production tested.  
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.  
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.  
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter  
capacitor shown in Figure 2).  
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable  
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.  
Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC  
frequency range for each possible configuration.  
FREQ_SEL  
Level  
Feedback  
Output  
Q/2  
Allowable SYNC Input  
FrequencyRange(MHZ)  
10to(2x_QfMAX Spec)/4  
20 to (2x_Q fMAX Spec)/2  
20 to (2x_Q fMAX Spec)/2  
40 to (2x_Q fMAX Spec)  
5 to (2x_Q fMAX Spec)/8  
10 to (2x_QfMAX Spec)/4  
10 to (2x_QfMAX Spec)/4  
20 to (2x_Q fMAX Spec)/2  
Corresponding 2Q Output  
FrequencyRange  
Phase Relationship of the Q Outputs  
to Rising SYNC Edge  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
0°  
0°  
Any Q (Q0-Q4)  
Q5  
180°  
0°  
2X_Q  
Q/2  
0°  
LOW  
Any Q (Q0-Q4)  
Q5  
0°  
LOW  
180°  
0°  
LOW  
2X_Q  
5
12345678...10

中文翻译

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