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74FCT388915T133J PDF预览

74FCT388915T133J

更新时间: 2024-01-24 21:15:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路输出元件
页数 文件大小 规格书
10页 154K
描述
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

74FCT388915T133J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.73系列:FCT
输入调节:MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:1
端子数量:28实输出次数:7
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.35 ns
座面最大高度:2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mm最小 fmax:133 MHz
Base Number Matches:1

74FCT388915T133J 数据手册

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IDT74FCT388915T  
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)  
COMMERCIALTEMPERATURERANGE  
PINCONFIGURATION  
1
2
3
28  
27  
26  
GND  
Q5  
Q4  
4
3
2
1
28 27 26  
VCC  
2Q  
25 Q/2  
FEEDBK  
REF_SEL  
SYNC(0)  
VCC(AN)  
LF  
5
VCC  
4
OE/RST  
FEEDBACK  
REF_SEL  
SYNC(0)  
VCC(AN)  
LF  
25  
24  
23  
Q/2  
GND  
Q3  
GND  
24  
6
5
23 Q3  
7
6
7
22  
21  
20  
19  
18  
17  
VCC  
VCC  
8
22  
21  
20  
19  
8
Q2  
Q2  
9
9
GND  
LOCK  
GND(AN)  
10  
11  
12  
10  
11  
GND  
LOCK  
GND(AN)  
SYNC(1)  
SYNC(1)  
FREQ_SEL  
GND  
PLL_EN  
GND  
12 13 14 15 16 17 18  
13  
14  
16  
15  
Q1  
VCC  
Q0  
SSOP  
PLCC  
TOP VIEW  
TOP VIEW  
PINDESCRIPTION  
Pin Name  
SYNC(0)  
SYNC(1)  
REF_SEL  
FREQ_SEL  
FEEDBACK  
LF  
I/O  
I
Description  
Referenceclockinput  
Referenceclockinput  
I
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)  
Selectsbetween÷1and÷2frequencyoptions(refertofunctionalblockdiagram)  
Feedbackinputtophasedetector  
I
I
I
Inputforexternalloopfilterconnection  
Q0-Q4  
O
O
O
O
O
I
Clockoutput  
Q5  
Invertedclockoutput  
2Q  
Clock output (2 x Q frequency)  
Q/2  
Clock output (Q frequency ÷ 2)  
LOCK  
Indicates phase lock has been achieved (HIGH when locked)  
OE/RST  
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in  
HIGH impedance.  
PLL_EN  
I
Disablesphase-lockforlowfrequencytesting(refertofunctionalblockdiagram)  
2

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