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74F280SCX

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74F280SCX 数据手册

April 1988

Revised September 2000

74F280

9-Bit Parity Generator/Checker

General Description

The F280 is a high-speed parity generator/checker that

accepts nine bits of input data and detects whether an

even or an odd number of these inputs is HIGH. If an even

number of inputs is HIGH, the Sum Even output is HIGH. If

an odd number is HIGH, the Sum Even output is LOW. The

Sum Odd output is the complement of the Sum Even out-

put.

Ordering Code:

Order Number Package Number

Package Description

74F280SC

74F280SJ

74F280PC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009512

www.fairchildsemi.com

12 3 4 5 6

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型号	品牌	获取价格	描述	数据表
74F280SCX_NL	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, PDSO14, 0.150 I
74F280SDC	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, CDIP14, SLIM, C
74F280SDCQR	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, CDIP14, SLIM, C
74F280SJ	FAIRCHILD	获取价格	9-Bit Parity Generator/Checker
74F280SJ	NSC	获取价格	9-Bit Parity Generator/Checker
74F280SJC	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, PDSO14, 0.300 I
74F280SJCX	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, PDSO14, 0.300 I
74F280SJX	ETC	获取价格	Parity Generator/Checker
74F280SJX_NL	FAIRCHILD	获取价格	Parity Generator/Checker, TTL, PDSO14,
74F280VC	FAIRCHILD	获取价格	Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, PDSO14, 0.300 I