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74F280SJX_NL PDF预览

74F280SJX_NL

更新时间: 2024-11-26 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 76K
描述
Parity Generator/Checker, TTL, PDSO14,

74F280SJX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP14,.3Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G14
逻辑集成电路类型:PARITY GENERATOR/CHECKER端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
认证状态:Not Qualified子类别:Arithmetic Circuits
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

74F280SJX_NL 数据手册

 浏览型号74F280SJX_NL的Datasheet PDF文件第2页浏览型号74F280SJX_NL的Datasheet PDF文件第3页浏览型号74F280SJX_NL的Datasheet PDF文件第4页浏览型号74F280SJX_NL的Datasheet PDF文件第5页浏览型号74F280SJX_NL的Datasheet PDF文件第6页 
April 1988  
Revised September 2000  
74F280  
9-Bit Parity Generator/Checker  
General Description  
The F280 is a high-speed parity generator/checker that  
accepts nine bits of input data and detects whether an  
even or an odd number of these inputs is HIGH. If an even  
number of inputs is HIGH, the Sum Even output is HIGH. If  
an odd number is HIGH, the Sum Even output is LOW. The  
Sum Odd output is the complement of the Sum Even out-  
put.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F280SC  
74F280SJ  
74F280PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009512  
www.fairchildsemi.com  

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