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74F273SJ PDF预览

74F273SJ

更新时间: 2024-11-24 22:35:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 63K
描述
Octal D-Type Flip-Flop

74F273SJ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
系列:F/FASTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:130000000 Hz最大I(ol):0.02 A
湿度敏感等级:1位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):56 mA传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
最小 fmax:130 MHzBase Number Matches:1

74F273SJ 数据手册

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April 1988  
Revised August 1999  
74F273  
Octal D-Type Flip-Flop  
General Description  
Features  
Ideal buffer for MOS microprocessor or memory  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The 74F273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
Buffered, asynchronous Master Reset  
See 74F377 for clock enable version  
See 74F373 for transparent latch version  
See 74F374 for 3-STATE version  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F273SC  
74F273SJ  
74F273PC  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009511  
www.fairchildsemi.com  

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