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74F273SCX PDF预览

74F273SCX

更新时间: 2024-11-24 23:24:07
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 74K
描述
Octal D-Type Flip-Flop

74F273SCX 数据手册

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April 1988  
Revised September 2000  
74F273  
Octal D-Type Flip-Flop  
General Description  
Features  
Ideal buffer for MOS microprocessor or memory  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The 74F273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
Buffered, asynchronous Master Reset  
See 74F377 for clock enable version  
See 74F373 for transparent latch version  
See 74F374 for 3-STATE version  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F273SC  
74F273SJ  
74F273PC  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009511  
www.fairchildsemi.com  

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