Datasheet > 逻辑 > 计数器> 74F191PMQB

74F191PMQB

更新时间： 2024-02-20 11:35:48

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器时钟
页数	文件大小	规格书
12页	185K
描述
Up/Down Binary Counter with Preset and Ripple Clock

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技术参数
数据手册

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74F191PMQB 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.28	Is Samacsys：	N
其他特性：	TCO OUTPUT	计数方向：	BIDIRECTIONAL
系列：	F/FAST	JESD-30 代码：	R-PDIP-T16
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
传播延迟（tpd）：	12 ns	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	最小 fmax：	125 MHz
Base Number Matches：	1

74F191PMQB 数据手册

Unit Loading/Fan Out

U.L.

Input I / I

IH IL

Pin Names

Description

HIGH / LOW

Output I / I

OH OL

Count Enable Input (Active LOW)

Clock Pulse Input (Active Rising Edge)

Parallel Data Inputs

1.0 / 3.0

1.0 / 1.0

50 / 33.3

20µA / -1.8mA

20µA / -0.6 mA

20µA / -0.6mA

-1mA / 20mA

P –P

Asynchronous Parallel Load Input (Active LOW)

Up/Down Count Control Input

Flip-Flop Outputs

U/D

Q –Q

Ripple Clock Output (Active LOW)

Terminal Count Output (Active HIGH)

Functional Description

The 74F191 is a synchronous up/down 4-bit binary

counter. It contains four edge-triggered flip-flops, with

internal gating and steering logic to provide individual

preset, count-up and count-down operations.

the design of multistage counters, as indicated in Figure

1 and Figure 2. In Figure 1, each RC output is used as

the clock input for the next higher stage. This configura-

tion is particularly advantageous when the clock source

has a limited drive capability, since it drives only the first

stage. To prevent counting in all stages it is only neces-

sary to inhibit the first stage, since a HIGH signal on CE

inhibits the RC output pulse, as indicated in the RC Truth

Table. A disadvantage of this configuration, in some

applications, is the timing skew between state changes

in the first and last stages. This represents the cumula-

tive delay of the clock as it ripples through the preceding

stages.

Each circuit has an asynchronous parallel load capability

permitting the counter to be preset to any desired num-

ber. When the Parallel Load (PL) input is LOW, informa-

tion present on the Parallel Data inputs (P –P ) is loaded

into the counter and appears on the Q outputs. This

operation overrides the counting functions, as indicated

in the Mode Select Table.

A HIGH signal on the CE input inhibits counting. When

CE is LOW, internal state changes are initiated synchro-

nously by the LOW-to-HIGH transition of the clock input.

The direction of counting is determined by the U/D input

signal, as indicated in the Mode Select Table. CE and

U/D can be changed with the clock in either state, pro-

vided only that the recommended setup and hold times

are observed.

A method of causing state changes to occur simulta-

neously in all stages is shown in Figure 2. All clock

inputs are driven in parallel and the RC outputs propa-

gate the carry/borrow signals in ripple fashion. In this

configuration the LOW state duration of the clock must

be long enough to allow the negative-going edge of the

carry/borrow signal to ripple through to the last stage

before the clock goes HIGH. There is no such restriction

on the HIGH state duration of the clock, since the RC

output of any device goes HIGH shortly after its CP input

goes HIGH.

Two types of outputs are provided as overflow/underflow

indicators. The Terminal Count (TC) output is normally

LOW and goes HIGH when a circuit reaches zero in the

count-down mode or reaches 15 in the count-up mode.

The TC output will then remain HIGH until a state

change occurs, whether by counting or presetting or until

U/D is changed. The TC output should not be used as a

clock signal because it is subject to decoding spikes.

The configuration shown in Figure 3 avoids ripple delays

and their associated restrictions. The CE input for a

given stage is formed by combining the TC signals from

all the preceding stages. Note that in order to inhibit

counting an enable signal must be included in each carry

gate. The simple inhibit scheme of Figure 1 and Figure 2

doesn’t apply, because the TC output of a given stage is

not affected by its own CE.

The TC signal is also used internally to enable the Ripple

Clock (RC) output. The RC output is normally HIGH.

When CE is LOW and TC is HIGH, the RC output will go

LOW when the clock next goes LOW and will stay LOW

until the clock goes HIGH again. This feature simplifies

74F191 Rev. 1.0.2

www.fairchildsemi.com

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与74F191PMQB相关器件

型号	品牌	描述	获取价格	数据表
74F191PMX	FAIRCHILD	Up/Down Binary Counter with Preset and Ripple Clock	获取价格
74F191QC	FAIRCHILD	Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,	获取价格
74F191SC	FAIRCHILD	Up/Down Binary Counter with Preset and Ripple Clock	获取价格
74F191SC	NSC	Up/Down Binary Counter with Preset and Ripple Clock	获取价格
74F191SC_NL	FAIRCHILD	Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,	获取价格
74F191SCQB	FAIRCHILD	Up/Down Binary Counter with Preset and Ripple Clock	获取价格

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