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74F192_00 PDF预览

74F192_00

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器时钟
页数 文件大小 规格书
7页 87K
描述
Up/Down Decade Counter with Separate Up/Down Clocks

74F192_00 数据手册

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April 1988  
Revised September 2000  
74F192  
Up/Down Decade Counter  
with Separate Up/Down Clocks  
General Description  
Features  
Guaranteed 4000V minimum ESD protection  
The 74F192 is an up/down BCD decade (8421) counter.  
Separate Count Up and Count Down Clocks are used, and  
in either counting mode the circuits operate synchronously.  
The outputs change state synchronously with the  
LOW-to-HIGH transitions on the clock inputs.  
Separate Terminal Count Up and Terminal Count Down  
outputs are used as the clocks for a subsequent stage  
without extra logic, thus simplifying multistage counter  
designs. Individual preset inputs allow the circuit to be used  
as a programmable counter. Both the Parallel Load (PL)  
and the Master Reset (MR) inputs asynchronously override  
the clocks.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F192SJ  
(Note 1)  
M16D  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74F192PC  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Note 1: Device not available in Tape and Reel.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009496  
www.fairchildsemi.com  

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