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74F169PCQB PDF预览

74F169PCQB

更新时间: 2023-02-26 16:13:53
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
8页 141K
描述
F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, DIP-16

74F169PCQB 数据手册

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Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/9488–1  
TL/F/9488–2  
Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
HIGH/LOW Output I /I  
OH OL  
b
20 mA/ 0.6 mA  
CEP  
CET  
CP  
Count Enable Parallel Input (Active LOW)  
Count Enable Trickle Input (Active LOW)  
Clock Pulse Input (Active Rising Edge)  
Parallel Data Inputs  
1.0/1.0  
1.0/2.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33.3  
50/33.3  
b
20 mA/ 1.2 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
P P  
0
3
PE  
Parallel Enable Input (Active LOW)  
Up-Down Count Control Input  
Flip-Flop Outputs  
U/D  
b
b
Q Q  
0
1 mA/20 mA  
1 mA/20 mA  
3
TC  
Terminal Count Output (Active LOW)  
Functional Description  
The ’F169 uses edge-triggered J-K type flip-flops and has  
no constraints on changing the control or data input signals  
in either state of the clock. The only requirement is that the  
various inputs attain the desired state at least a setup time  
before the rising edge of the clock and remain valid for the  
recommended hold time thereafter. The parallel load opera-  
tion takes precedence over other operations, as indicated in  
the Mode Select Table. When PE is LOW, the data on the  
P P inputs enters the flip-flops on the next rising edge of  
CET is LOW, when a counter reaches zero in the Count  
Down mode or reaches 15 for the ’F169 in the Count Up  
mode. The TC output state is not a function of the Count  
Enable Parallel (CEP) input level. Since the TC signal is de-  
rived by decoding the flip-flop states, there exists the possi-  
bility of decoding spikes on TC. For this reason the use of  
TC as a clock signal is not recommended (see logic equa-  
tions below).  
e
0
3
1) Count Enable  
CEP CET PE  
#
#
the clock. In order for counting to occur, both CEP and CET  
must be LOW and PE must be HIGH; the U/D input then  
determines the direction of counting. The Terminal Count  
(TC) output is normally HIGH and goes LOW, provided that  
e
2) Up: (’F169): TC  
Q
Q
Q
Q
Q
Q
#
3
(Down) CET  
#
(Up) CET  
#
#
#
#
#
#
#
0
1
2
e
3) Down: TC  
Q
Q
#
0
1
2
3
2

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