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74F161ASCX

更新时间： 2024-01-05 11:44:25
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 863K
描述
Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, 0.150 INCH, MS-012, SOIC-16

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74F161ASCX 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.62计数方向：UP
系列：F/FASTJESD-30 代码：R-PDSO-G16
长度：9.9 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：11 ns
座面最大高度：1.753 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：90 MHzBase Number Matches：1

74F161ASCX 数据手册

 浏览型号74F161ASCX的Datasheet PDF文件第1页浏览型号74F161ASCX的Datasheet PDF文件第2页浏览型号74F161ASCX的Datasheet PDF文件第3页浏览型号74F161ASCX的Datasheet PDF文件第5页浏览型号74F161ASCX的Datasheet PDF文件第6页浏览型号74F161ASCX的Datasheet PDF文件第7页 
Logic Equations:  
Count Enable = CEP • CET • PE  
Functional Description  
The 74F161A and 74F163A count in modulo-16 binary  
sequence. From state 15 (HHHH) they increment to  
state 0 (LLLL). The clock inputs of all flip-flops are driven  
in parallel through a clock buffer. Thus all changes of the  
Q outputs (except due to Master Reset of the 74F161A)  
occur as a result of, and synchronous with, the LOW-to-  
HIGH transition of the CP input signal. The circuits have  
four fundamental modes of operation, in order of prece-  
dence: asynchronous reset (74F161A), synchronous  
reset (74F163A), parallel load, count-up and hold. Five  
control inputs—Master Reset (MR, 74F161A), Synchro-  
nous Reset (SR, 74F163A), Parallel Enable (PE), Count  
Enable Parallel (CEP) and Count Enable Trickle (CET)—  
determine the mode of operation, as shown in the Mode  
Select Table. A LOW signal on MR overrides all other  
inputs and asynchronously forces all outputs LOW. A  
LOW signal on SR overrides counting and parallel load-  
ing and allows all outputs to go LOW on the next rising  
edge of CP. A LOW signal on PE overrides counting and  
TC = Q • Q • Q • Q • CET  
0
1
2
3
Mode Select Table  
Action on the Rising  
(1)  
SR  
L
PE CET CEP  
Clock Edge (  
)
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)  
H
Load (P →Q )  
n
n
H
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
H
H
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
allows information on the Parallel Data (P ) inputs to be  
n
Note:  
1. For 74F163A only  
loaded into the flip-flops on the next rising edge of CP.  
With PE and MR ('F161A) or SR (74F163A) HIGH, CEP  
and CET permit counting when both are HIGH. Con-  
versely, a LOW signal on either CEP or CET inhibits  
counting.  
State Diagram  
The 74F161A and 74F163A use D-type edge triggered  
flip-flops and changing the SR, PE, CEP and CET inputs  
when the CP is in either state does not cause errors, pro-  
vided that the recommended setup and hold times, with  
respect to the rising edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and the counter is in state 15. To implement syn-  
chronous multi-stage counters, the TC outputs can be  
used with the CEP and CET inputs in two different ways.  
Please refer to the 74F568 data sheet. The TC output is  
subject to decoding spikes due to internal race condi-  
tions and is therefore not recommended for use as a  
clock or asynchronous reset for flip-flops, counters or  
registers.  
©1988 Fairchild Semiconductor Corporation  
74F161A, 74F163A Rev. 1.0.2  
www.fairchildsemi.com  
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