Philips Semiconductors
Product specification
18-bit buffer/driver (3-State)
74ALVCH16825
FEATURES
PIN CONFIGURATION
• Wide supply voltage range of 1.2V to 3.6V
1OE1
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE2
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
1Y
1Y
1A
1
1
0
1
3
1A
GND
4
GND
1Y
2
5
1A
2
1Y
6
1A
3
3
TM
• MULTIBYTE flow-through standard pin-out architecture
V
7
V
CC
CC
• Low inductance multiple V and GND pins for minimum noise
CC
1Y
8
1A
1A
1A
4
5
6
4
5
6
and ground bounce
1Y
1Y
9
• All data inputs have bus hold
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
GND
• Output drive capability 50Ω transmission lines @ 85°C
1Y
1Y
1A
1A
7
8
7
8
DESCRIPTION
The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with
3-State outputs for bus-oriented applications.
GND
GND
GND
GND
2Y
2Y
2A
2A
0
1
0
1
The 74ALVCH16825 consists of two 9-bit sections with separate
output enable signals. For either 9-bit buffer section, the two output
enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
LOW for corresponding D outputs to be active. If either output
enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.
GND
GND
2Y
2Y
2Y
2A
2A
2A
V
2
3
4
2
3
4
V
The 74ALVCH16825 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
CC
CC
2Y
2A
5
6
5
6
2Y
2A
GND
2Y
GND
2A
2A
7
7
8
2Y
8
2OE1
2OE2
SH00139
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t ≤ 2.5ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
ns
Propagation delay
CP to Qn
V
CC
V
CC
= 2.5V, C = 30pF
= 3.3V, C = 50pF
2.0
2.0
L
L
t
/t
PHL PLH
C
C
Input capacitance
4.0
19
3
pF
I
Output enabled
Output disabled
1
Power dissipation capacitance per latch
V = GND to V
I CC
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW):
PD
D
2
2
P
= C × V
× f + S (C × V
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;
CC o i L
D
PD
CC
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V
o
× f ) = sum of outputs.
o
CC
L
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
DRAWING
NUMBER
NORTH AMERICA
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
–40°C to +85°C
74ALVCH16825 DGG
ACH16825 DGG
SOT364-1
2
1998 Jul 27
853-2097 19785