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74ALVCH16827DLRG4 PDF预览

74ALVCH16827DLRG4

更新时间： 2024-01-08 19:49:16
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 300K
描述
20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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74ALVCH16827DLRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：0.300 INCH, GREEN, PLASTIC, SSOP-56针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56Is Samacsys：N
其他特性：WITH DUAL OUTPUT ENABLE系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：4.1 ns认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.49 mmBase Number Matches：1

74ALVCH16827DLRG4 数据手册

 浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第2页浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第3页浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第4页浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第5页浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第6页浏览型号74ALVCH16827DLRG4的Datasheet PDF文件第7页 
SN74ALVCH16827  
20-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES041D–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE1  
1Y1  
1OE2  
1A1  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
3
1Y2  
1A2  
ESD Protection Exceeds 2000 V Per  
4
GND  
1Y3  
GND  
1A3  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
5
6
1Y4  
1A4  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1Y5  
1Y6  
1Y7  
GND  
1Y8  
1Y9  
1Y10  
2Y1  
2Y2  
2Y3  
GND  
2Y4  
2Y5  
2Y6  
1A5  
1A6  
1A7  
GND  
1A8  
1A9  
1A10  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
DESCRIPTION  
This 20-bit noninverting buffer/driver is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16827 is composed of two 10-bit  
sections with separate output-enable signals. For  
either 10-bit buffer section, the two output-enable  
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
both be low for the corresponding Y outputs to be  
active. If either output-enable input is high, the  
outputs of that 10-bit buffer section are in the  
high-impedance state.  
V
CC  
V
CC  
2Y7  
2Y8  
2A7  
2A8  
GND  
2Y9  
2Y10  
2OE1  
GND  
2A9  
2A10  
2OE2  
To ensure the high-impedance state during power up  
or power down, OE should be tied to VCC through a  
pullup resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
Active bus-hold circuitry is provided to hold unused or  
floating data inputs at a valid logic level.  
The SN74ALVCH16827 is characterized for operation  
from -40°C to 85°C.  
FUNCTION TABLE  
(each 10-bit section)  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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