Datasheet > 74AHCT86PW,112

74AHCT86PW,112

更新时间： 2024-10-01 06:52:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	86K
描述
74AHC(T)86 - Quad 2-input EXCLUSIVE-OR gate TSSOP 14-Pin

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74AHCT86PW,112 数据手册

74AHC86; 74AHCT86

Quad 2-input EXCLUSIVE-OR gate

Rev. 02 — 15 November 2007

Product data sheet

1. General description

The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard no. 7A.

The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function.

2. Features

■ Balanced propagation delays

■ All inputs have a Schmitt-trigger action

■ Inputs accepts voltages higher than V_CC

■ For 74AHC86 only: operates with CMOS input levels

■ For 74AHCT86 only: operates with TTL input levels

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range

−40 °C to +125 °C

Name

Description

Version

74AHC86D

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHCT86D

74AHC86PW

74AHCT86PW

74AHC86BQ

74AHCT86BQ

−40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

12 3 4 5 6 7...14

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