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74ACTQ574DCQR PDF预览

74ACTQ574DCQR

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
12页 209K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20

74ACTQ574DCQR 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69系列:ACT
JESD-30 代码:R-GDIP-T20长度:24.51 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

74ACTQ574DCQR 数据手册

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March 1993  
74ACQ574 54ACTQ/74ACTQ574  
#
Quiet Series Octal D Flip-Flop  
with TRI-STATE Outputs  
É
General Description  
Features  
Y
I
and I  
reduced by 50%  
The ’ACQ/’ACTQ574 is a high-speed, low-power octal D-  
type flip-flop with a buffered Common Clock (CP) and a buff-  
ered common Output Enable (OE). The information present-  
ed to the D inputs is stored in the flip-flops on the LOW-to-  
HIGH clock (CP) transition.  
CC  
OZ  
Y
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Y
Y
Guaranteed pin-to-pin skew AC performance  
Inputs and outputs on opposite sides of the package  
allowing easy interface with microprocessors  
Functionally identical to the ’ACQ/ACTQ374  
TRI-STATE outputs drive bus lines or buffer memory  
address registers  
’ACQ/’ACTQ574 utilizes Quiet Series technology to guaran-  
tee quiet output switching and improve dynamic threshold  
performance. FACT Quiet SeriesTM features GTOTM output  
control and undershoot corrector in addition to  
ground bus for superior performance.  
Y
Y
a split  
Y
Y
Y
Y
Outputs source/sink 24 mA  
The ’ACQ/’ACTQ574 is functionally identical to the  
’ACTQ374 but with different pin-out.  
Faster prop delays than the standard ’AC/’ACT574  
4 kV minimum ESD immunity  
Standard Military Drawing (SMD)  
Ð ’ACTQ574: 5962-8960102  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, Flatpak and SOIC  
IEEE/IEC  
TL/F/10634–1  
TL/F/10634–3  
TL/F/10634–2  
Pin Assignment  
for LCC  
Pin Names  
Description  
Data Inputs  
D D  
0
7
CP  
OE  
Clock Pulse Input  
TRI-STATE Output Enable Input  
TRI-STATE Outputs  
O O  
0
7
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM, FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation.  
TL/F/10634–4  
C
1995 National Semiconductor Corporation  
TL/F/10634  
RRD-B30M75/Printed in U. S. A.  

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