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74ACT163SC_NL PDF预览

74ACT163SC_NL

更新时间： 2024-02-23 15:00:09
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 114K
描述
Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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74ACT163SC_NL 技术参数

生命周期：Contact Manufacturer包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61计数方向：UP
系列：ACTJESD-30 代码：R-PDSO-G16
长度：5 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：11 ns
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：4.4 mm
最小 fmax：105 MHzBase Number Matches：1

74ACT163SC_NL 数据手册

 浏览型号74ACT163SC_NL的Datasheet PDF文件第1页浏览型号74ACT163SC_NL的Datasheet PDF文件第3页浏览型号74ACT163SC_NL的Datasheet PDF文件第4页浏览型号74ACT163SC_NL的Datasheet PDF文件第5页浏览型号74ACT163SC_NL的Datasheet PDF文件第6页浏览型号74ACT163SC_NL的Datasheet PDF文件第7页 
Logic Symbols  
Functional Description  
The AC/ACT163 counts in modulo-16 binary sequence.  
From state 15 (HHHH) it increments to state 0 (LLLL). The  
clock inputs of all flip-flops are driven in parallel through a  
clock buffer. Thus all changes of the Q outputs occur as a  
result of, and synchronous with, the LOW-to-HIGH transi-  
tion of the CP input signal. The circuits have four funda-  
mental modes of operation, in order of precedence:  
synchronous reset, parallel load, count-up and hold. Four  
control inputs—Synchronous Reset (SR), Parallel Enable  
(PE), Count Enable Parallel (CEP) and Count Enable  
Trickle (CET)—determine the mode of operation, as shown  
in the Mode Select Table. A LOW signal on SR overrides  
counting and parallel loading and allows all outputs to go  
LOW on the next rising edge of CP. A LOW signal on PE  
overrides counting and allows information on the Parallel  
Data (Pn) inputs to be loaded into the flip-flops on the next  
IEEE/IEC  
rising edge of CP. With PE and SR HIGH, CEP and CET  
permit counting when both are HIGH. Conversely, a LOW  
signal on either CEP or CET inhibits counting.  
The AC/ACT163 uses D-type edge-triggered flip-flops and  
changing the SR, PE, CEP and CET inputs when the CP is  
in either state does not cause errors, provided that the rec-  
ommended setup and hold times, with respect to the rising  
edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and counter is in state 15. To implement synchro-  
nous multistage counters, the TC outputs can be used with  
the CEP and CET inputs in two different ways.  
Mode Select Table  
Figure 1 shows the connections for simple ripple carry, in  
which the clock period must be longer than the CP to TC  
delay of the first stage, plus the cumulative CET to TC  
delays of the intermediate stages, plus the CET to CP  
setup time of the last stage. This total delay plus setup time  
sets the upper limit on clock frequency. For faster clock  
rates, the carry lookahead connections shown in Figure 2  
are recommended. In this scheme the ripple delay through  
the intermediate stages commences with the same clock  
that causes the first stage to tick over from max to min in  
the Up mode, or min to max in the Down mode, to start its  
final cycle. Since this final cycle takes 16 clocks to com-  
plete, there is plenty of time for the ripple to progress  
through the intermediate stages. The critical timing that lim-  
its the clock period is the CP to TC delay of the first stage  
plus the CEP to CP setup time of the last stage. The TC  
output is subject to decoding spikes due to internal race  
conditions and is therefore not recommended for use as a  
clock or asynchronous reset for flip-flops, registers or  
counters.  
SR  
PE  
CET  
CEP  
Action on the Rising  
Clock Edge (  
Reset (Clear)  
Load (Pn → Qn)  
)
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Logic Equations: Count Enable = CEP • CET • PE  
TC = Q0 • Q1 • Q2 • Q3 • CET  
www.fairchildsemi.com  
2
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