74AC377

更新时间： 2024-01-12 10:32:17

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器时钟
页数	文件大小	规格书
9页	103K
描述
Octal D-Type Flip-Flop with Clock Enable

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AC377 数据手册

November 1988

Revised November 1999

74AC377 • 74ACT377

Octal D-Type Flip-Flop with Clock Enable

General Description

Features

The AC/ACT377 has eight edge-triggered, D-type flip-flops

with individual D inputs and Q outputs. The common buff-

ered Clock (CP) input loads all flip-flops simultaneously,

when the Clock Enable (CE) is LOW.

■ I_CCreduced by 50%

■ Ideal for addressable register applications

■ Clock enable for address and data synchronization

applications

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

The CE input must be stable only one setup time prior to

the LOW-to-HIGH clock transition for predictable operation.

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Outputs source/sink 24 mA

■ See 273 for master reset version

■ See 373 for transparent latch version

■ See 374 for 3-STATE version

■ ACT377 has TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74AC377SC

74AC377SJ

M20B

M20D

MTC20

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC377MTC

74AC377PC

74ACT377SC

74ACT377SJ

74ACT377MTC

74ACT377PC

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M20B

M20D

MTC20

N20A

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

D₀–D₇

Description

Data Inputs

Clock Enable (Active LOW)

Data Outputs

Q₀–Q₇

Clock Pulse Input

FACT is a trademark of Fairchild Semiconductor Corporation.

DS009961

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

下载PDF

与74AC377相关器件

型号	品牌	获取价格	描述	数据表
74AC377_08	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74AC377FCQR	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20,
74AC377FCT	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20,
74AC377FCTR	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20,
74AC377LC	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20,
74AC377LC	TI	获取价格	AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
74AC377LCQR	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20,
74AC377LCQR	TI	获取价格	AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
74AC377LCT	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20,
74AC377LCTR	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20,

与74AC377相关文章

芯片底部填充工艺：提升电子设备可靠性的关键步骤
2024-08-14

54
REF03GPZ资料解读：主要特征、技术参数、应用场景
2024-08-05

124
一文带你了解DS28E40主要特征、安全特性、应用场景
2024-07-30

170
RT9172资料手册解读：关节特性、引脚信息、参数说明
2024-07-30

152

产品中心

服务支持

精选活动

关于我们

帮助中心

74AC377

74AC377 数据手册

与74AC377相关器件

与74AC377相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74AC377

74AC377 数据手册

与74AC377相关器件

与74AC377相关文章

您还可以找

您在本页遇到什么问题？