July 1988
Revised March 2005
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
Features
■ ICC and IOZ reduced by 50%
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional out-
puts are provided for flip-flops Q0, Q7 to allow easy serial
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load
and store
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
cascading. A separate active LOW Master Reset is used to
reset the register.
■ ACT299 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC299SC
M20B
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC299SCX_NL
(Note 1)
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74AC299SJ
M20D
MTC20
N20A
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74AC299MTC
74AC299PC
74ACT299SC
74ACT299MTC
74ACT299PC
M20B
MTC20
N20A
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
Description
CP
Clock Pulse Input
DS0
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
DS7
S0, S1
MR
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or
OE1, OE2
I/O0–I/O7
3-STATE Parallel Outputs
Serial Outputs
Q0, Q7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009893
www.fairchildsemi.com