5秒后页面跳转
74AC11086DRE4 PDF预览

74AC11086DRE4

更新时间: 2024-01-07 09:42:30
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路石英晶振触发器
页数 文件大小 规格书
5页 82K
描述
Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85

74AC11086DRE4 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SO-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65Is Samacsys:N
其他特性:CENTER PIN VCC AND GND系列:AC
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.064 A功能数量:4
输入次数:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
Prop。Delay @ Nom-Sup:10.6 ns传播延迟(tpd):6.8 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74AC11086DRE4 数据手册

 浏览型号74AC11086DRE4的Datasheet PDF文件第1页浏览型号74AC11086DRE4的Datasheet PDF文件第3页浏览型号74AC11086DRE4的Datasheet PDF文件第4页浏览型号74AC11086DRE4的Datasheet PDF文件第5页 
74AC11086  
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE  
SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996  
logic diagram (positive logic)  
1
1A  
2
3
1Y  
2Y  
16  
1B  
15  
2A  
14  
2B  
11  
3A  
6
7
3Y  
4Y  
10  
3B  
9
4A  
8
4B  
exclusive-OR logic  
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.  
EXCLUSIVE OR  
= 1  
These are five equivalent exclusive-OR symbols valid for a 74AC11086 gate in positive logic; negation may be shown  
at any two ports.  
EVEN-PARITY ELEMENT  
ODD-PARITY ELEMENT  
LOGIC-IDENTITY ELEMENT  
=
2k  
2k+1  
The output is active (high) if  
all inputs stand at the same  
logic level (i.e., A=B).  
The output is active (high) if  
an even number of inputs  
(i.e., 0 or 2) are active (high).  
The output is active (high) if an  
odd number of inputs (i.e., only  
1 of the 2) are active (high).  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
Continuous current through V  
Maximum power dissipation at T = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA  
A
N package . . . . . . . . . . . . . . . . . . . . 1.1 W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,  
except for the N package, which has a trace length of zero.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与74AC11086DRE4相关器件

型号 品牌 描述 获取价格 数据表
74AC11086D-T YAGEO XOR Gate, AC Series, 4-Func, 2-Input, CMOS, PDSO16

获取价格

74AC11086N TI QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

获取价格

74AC11086N YAGEO XOR Gate, AC Series, 4-Func, 2-Input, CMOS, PDIP16

获取价格

74AC11086NE4 TI Quadruple 2-Input Exclusive-OR Gates 16-PDIP -40 to 85

获取价格

74AC11109 TI DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

获取价格

74AC11109D TI Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85

获取价格