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74ABT162823ADGGRG4 PDF预览

74ABT162823ADGGRG4

更新时间: 2022-10-12 16:33:20
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
10页 180K
描述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

74ABT162823ADGGRG4 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢉ ꢋ ꢄꢌ ꢀꢁ ꢍꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢉꢋ ꢄ  
ꢇ ꢊ ꢎꢅꢏ ꢆ ꢅꢐꢀ ꢎꢏꢁꢆ ꢑꢒꢓꢄꢔꢑ ꢓ ꢕꢏ ꢖ ꢎꢓ ꢕꢗ ꢖꢀ  
ꢘ ꢏꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗ ꢐꢆ ꢖꢐ ꢆꢀ  
SCBS666B − JULY 1996 − REVISED JUNE 2004  
SN54ABT162823A . . . WD PACKAGE  
SN74ABT162823A . . . DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
Members of the Texas Instruments  
WidebusFamily  
Output Ports Have Equivalent 25-Series  
Resistors So No External Resistors Are  
Required  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1CLR  
1OE  
1Q1  
GND  
1Q2  
1Q3  
1CLK  
1CLKEN  
1D1  
GND  
1D2  
2
D
D
D
D
D
Typical V  
(Output Ground Bounce)  
OLP  
3
<1 V at V  
= 5 V, T = 25°C  
4
CC  
A
5
High-Impedance State During Power Up  
and Power Down  
6
1D3  
7
V
V
I
and Power-Up 3-State Support Hot  
CC  
CC  
off  
8
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
Insertion  
9
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flow-Through Architecture Optimizes PCB  
Layout  
description/ordering information  
These 18-bit bus-interface flip-flops feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing wider buffer registers, I/O ports,  
bidirectional bus drivers with parity, and working  
registers.  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2OE  
2CLR  
2D7  
2D8  
GND  
2D9  
2CLKEN  
2CLK  
The ’ABT162823A devices can be used as two  
9-bit flip-flops or one 18-bit flip-flop. With the  
clock-enable (CLKEN) input low, the D-type  
flip-flops enter data on the low-to-high transitions  
of the clock. Taking CLKEN high disables the  
clock buffer, thus latching the outputs. Taking the  
clear (CLR) input low causes the Q outputs to go  
low independently of the clock.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74ABT162823ADL  
SSOP − DL  
ABT162823A  
Tape and reel  
SN74ABT162823ADLR  
SN74ABT162823ADGGR  
SNJ54ABT162823AWD  
−40°C to 85°C  
−55°C to 125°C  
TSSOP − DGG Tape and reel  
CFP − WD Tube  
ABT162823A  
SNJ54ABT162823AWD  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2004, Texas Instruments Incorporated  
ꢐ ꢁ ꢕꢑꢀꢀ ꢗ ꢆꢙ ꢑꢒꢘ ꢏꢀ ꢑ ꢁ ꢗꢆꢑꢚ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢖꢒ ꢗ ꢚ ꢐ ꢔꢆ ꢏꢗ ꢁ  
ꢩꢦ ꢨ ꢦ ꢣ ꢤ ꢛ ꢤ ꢨ ꢞ ꢬ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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