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74HC40103DB PDF预览

74HC40103DB

更新时间： 2024-02-29 11:26:51
品牌 Logo 应用领域
矽成 - ICSI 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 140K
描述
8-bit synchronous binary down counter

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74HC40103DB 技术参数

Source Url Status Check Date：2013-06-14 00:00:00是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
其他特性：TCO OUTPUT; RESET TO MAX COUNT计数方向：DOWN
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：450 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：12 MHz
Base Number Matches：1

74HC40103DB 数据手册

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Philips Semiconductors  
Product specification  
8-bit synchronous binary down counter  
74HC/HCT40103  
Counting is inhibited when the terminal enable input (TE)  
is HIGH. The terminal count output (TC) goes LOW when  
the count reaches zero if TE is LOW, and remains LOW for  
one full clock period.  
FEATURES  
• Cascadable  
• Synchronous or asynchronous preset  
• Output capability: standard  
• ICC category: MSI  
When the synchronous preset enable input (PE) is LOW,  
data at the jam input (P0 to P7) is clocked into the counter  
on the next positive-going clock transition regardless of the  
state of TE. When the asynchronous preset enable input  
(PL) is LOW, data at the jam input (P0 to P7) is  
GENERAL DESCRIPTION  
The 74HC/HCT40103 are high-speed Si-gate CMOS  
devices and are pin compatible with the “40103” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
asynchronously forced into the counter regardless of the  
state of PE, TE, or CP. The jam inputs (P0 to P7) represent  
a single 8-bit binary word.  
When the master reset input (MR) is LOW, the counter is  
asynchronously cleared to its maximum count (decimal  
255) regardless of the state of any other input. The  
precedence relationship between control inputs is  
indicated in the function table.  
The 74HC/HCT40103 consist each of an 8-bit  
synchronous down counter with a single output which is  
active when the internal count is zero. The “40103”  
contains a single 8-bit binary counter and has control  
inputs for enabling or disabling the clock (CP), for clearing  
the counter to its maximum count, and for presetting the  
counter either synchronously or asynchronously. All  
control inputs and the terminal count output (TC) are  
active-LOW logic.  
If all control inputs except TE are HIGH at the time of zero  
count, the counters will jump to the maximum count, giving  
a counting sequence of 256 clock pulses long.  
The “40103” may be cascaded using the TE input and the  
TC output, in either a synchronous or ripple mode.  
In normal operation, the counter is decremented by one  
count on each positive-going transition of the clock (CP).  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL PARAMETER  
CONDITIONS  
UNIT  
HC  
HCT  
tPHL/ tPLH propagation delay CP to TC  
CL = 15 pF; VCC = 5 V  
30  
32  
30  
31  
ns  
fmax  
CI  
maximum clock frequency  
input capacitance  
MHz  
pF  
3.5  
24  
3.5  
27  
CPD  
power dissipation capacitance per package notes 1 and 2  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
∑ (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC − 1.5 V  
1998 Jul 08  
2
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